Searched refs:wptr_offs (Results 1 – 19 of 19) sorted by relevance
90 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; in amdgpu_ih_ring_init()95 r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs); in amdgpu_ih_ring_init()103 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); in amdgpu_ih_ring_init()136 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); in amdgpu_ih_ring_fini()
140 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()142 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()201 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()203 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
128 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); in vega10_ih_irq_init()130 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in vega10_ih_irq_init()199 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()201 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()
54 unsigned wptr_offs; member
79 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in si_ih_irq_init()107 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in si_ih_get_wptr()
134 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cik_ih_irq_init()190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cik_ih_get_wptr()
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cz_ih_irq_init()192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cz_ih_get_wptr()
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in iceland_ih_irq_init()192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in iceland_ih_get_wptr()
273 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()353 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
85 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
368 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()388 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()393 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()711 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
203 unsigned wptr_offs; member
301 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()332 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()338 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()706 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
121 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()740 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
2500 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()2659 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_kcq_enable()2796 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()3877 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()3892 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()4046 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()4157 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
4506 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()4651 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()4784 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()6293 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()6304 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()6468 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()6476 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
2649 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()2657 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()2957 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
4174 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()4190 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()8428 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()8440 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
865 unsigned wptr_offs; member
