Home
last modified time | relevance | path

Searched refs:speed_cntl (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/radeon/
Drv770.c2023 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2062 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2063 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in rv770_pcie_gen2_enable()
2064 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in rv770_pcie_gen2_enable()
2075 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2076 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in rv770_pcie_gen2_enable()
2077 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
2079 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in rv770_pcie_gen2_enable()
2080 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in rv770_pcie_gen2_enable()
2081 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in rv770_pcie_gen2_enable()
[all …]
Dr600.c4487 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4511 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4512 if (speed_cntl & LC_CURRENT_DATA_RATE) { in r600_pcie_gen2_enable()
4540 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4541 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
4542 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
4556 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
4557 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
4558 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
4559 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
[all …]
Devergreen.c5323 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5342 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5343 if (speed_cntl & LC_CURRENT_DATA_RATE) { in evergreen_pcie_gen2_enable()
5350 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || in evergreen_pcie_gen2_enable()
5351 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in evergreen_pcie_gen2_enable()
5357 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5358 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in evergreen_pcie_gen2_enable()
5359 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in evergreen_pcie_gen2_enable()
5361 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in evergreen_pcie_gen2_enable()
5362 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; in evergreen_pcie_gen2_enable()
[all …]
Dsi.c7087 u32 speed_cntl, current_data_rate; in si_pcie_gen3_enable() local
7111 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
7112 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in si_pcie_gen3_enable()
7218 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in si_pcie_gen3_enable()
7219 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in si_pcie_gen3_enable()
7220 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
7232 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
7233 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in si_pcie_gen3_enable()
7234 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
7237 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
[all …]
Dcik.c9504 u32 speed_cntl, current_data_rate; in cik_pcie_gen3_enable() local
9528 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
9529 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in cik_pcie_gen3_enable()
9635 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in cik_pcie_gen3_enable()
9636 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in cik_pcie_gen3_enable()
9637 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
9649 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
9650 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in cik_pcie_gen3_enable()
9651 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
9654 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
[all …]
Dsi_dpm.c5733 u32 speed_cntl; in si_get_current_pcie_speed() local
5735 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in si_get_current_pcie_speed()
5736 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in si_get_current_pcie_speed()
5738 return (u16)speed_cntl; in si_get_current_pcie_speed()
Dci_dpm.c4813 u32 speed_cntl = 0; in ci_get_current_pcie_speed() local
4815 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in ci_get_current_pcie_speed()
4816 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in ci_get_current_pcie_speed()
4818 return (u16)speed_cntl; in ci_get_current_pcie_speed()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dcik.c1381 u32 speed_cntl, current_data_rate; in cik_pcie_gen3_enable() local
1398 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1399 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> in cik_pcie_gen3_enable()
1511 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | in cik_pcie_gen3_enable()
1513 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; in cik_pcie_gen3_enable()
1514 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1526 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1527 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; in cik_pcie_gen3_enable()
1528 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1531 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
[all …]
Dsi.c1562 u32 speed_cntl, current_data_rate; in si_pcie_gen3_enable() local
1579 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
1580 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> in si_pcie_gen3_enable()
1681 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; in si_pcie_gen3_enable()
1682 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; in si_pcie_gen3_enable()
1683 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
1695 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
1696 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; in si_pcie_gen3_enable()
1697 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in si_pcie_gen3_enable()
1700 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in si_pcie_gen3_enable()
[all …]
Dci_dpm.c4964 u32 speed_cntl = 0; in ci_get_current_pcie_speed() local
4966 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) & in ci_get_current_pcie_speed()
4968 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; in ci_get_current_pcie_speed()
4970 return (u16)speed_cntl; in ci_get_current_pcie_speed()
Dsi_dpm.c6187 u32 speed_cntl; in si_get_current_pcie_speed() local
6189 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; in si_get_current_pcie_speed()
6190 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; in si_get_current_pcie_speed()
6192 return (u16)speed_cntl; in si_get_current_pcie_speed()