Searched refs:sclk_dpm_enable_mask (Results 1 – 14 of 14) sorted by relevance
166 uint32_t sclk_dpm_enable_mask; member
177 uint32_t sclk_dpm_enable_mask; member
155 uint32_t sclk_dpm_enable_mask; member
2616 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()2618 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()2655 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2658 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()2693 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_lowest()2695 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_force_dpm_lowest()3830 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in smu7_generate_dpm_level_enable_mask()4363 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); in smu7_force_clock_level()4937 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_patch_compute_profile_mode()4939 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_patch_compute_profile_mode()[all …]
110 u32 sclk_dpm_enable_mask; member
3303 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3821 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3824 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4176 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()4232 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()4234 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()4271 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()4273 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
111 u32 sclk_dpm_enable_mask; member
3448 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3968 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3971 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4325 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()4383 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()4385 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()4424 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()4426 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()6623 pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); in ci_dpm_force_clock_level()
908 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()913 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()
1057 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()
1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()
1019 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()
499 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
722 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()
