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Searched refs:plld (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/arch/powerpc/boot/
D4xx.c407 u32 plld = CPR0_READ(DCRN_CPR0_PLLD); in __ibm440eplike_fixup_clocks() local
410 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); in __ibm440eplike_fixup_clocks()
411 u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); in __ibm440eplike_fixup_clocks()
412 u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); in __ibm440eplike_fixup_clocks()
413 u32 lfbdv = __fix_zero(plld & 0x3f, 64); in __ibm440eplike_fixup_clocks()
731 u32 plld = CPR0_READ(DCRN_CPR0_PLLD); in ibm405ex_fixup_clocks() local
738 u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1)); in ibm405ex_fixup_clocks()
740 u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1)); in ibm405ex_fixup_clocks()
/Linux-v4.19/arch/arm/boot/dts/
Dwm8650.dtsi102 plld: plld { label
140 clocks = <&plld>;
Dwm8850.dtsi105 plld: plld { label
157 clocks = <&plld>;
Dwm8505.dtsi105 plld: plld { label
136 clocks = <&plld>;
Dwm8750.dtsi108 plld: plld { label
146 clocks = <&plld>;
/Linux-v4.19/drivers/clk/tegra/
Dclk-tegra210.c816 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) in tegra210_plld_set_defaults() argument
821 plld->params->defaults_set = true; in tegra210_plld_set_defaults()
823 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
831 _pll_misc_chk_default(clk_base, plld->params, 1, in tegra210_plld_set_defaults()
838 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
841 if (!plld->params->defaults_set) in tegra210_plld_set_defaults()
846 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
855 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
859 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
[all …]
/Linux-v4.19/drivers/gpu/drm/tegra/
Ddsi.c955 unsigned long plld; in tegra_dsi_encoder_atomic_check() local
984 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; in tegra_dsi_encoder_atomic_check()
985 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); in tegra_dsi_encoder_atomic_check()
1002 plld /= 2; in tegra_dsi_encoder_atomic_check()
1017 plld, scdiv); in tegra_dsi_encoder_atomic_check()