Searched refs:pch_pfit (Results 1 – 6 of 6) sorted by relevance
370 pipe_config->pch_pfit.force_thru = enable; in hsw_pipe_A_crc_wa()372 pipe_config->pch_pfit.enabled != enable) in hsw_pipe_A_crc_wa()
3855 if (new_crtc_state->pch_pfit.enabled) in intel_update_pipe_config()3858 if (new_crtc_state->pch_pfit.enabled) in intel_update_pipe_config()3860 else if (old_crtc_state->pch_pfit.enabled) in intel_update_pipe_config()4986 if (crtc->config->pch_pfit.enabled) { in skylake_pfit_enable()5003 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); in skylake_pfit_enable()5004 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); in skylake_pfit_enable()5014 if (crtc->config->pch_pfit.enabled) { in ironlake_pfit_enable()5024 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); in ironlake_pfit_enable()5025 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); in ironlake_pfit_enable()5685 intel_crtc->config->pch_pfit.enabled; in haswell_crtc_enable()[all …]
166 pipe_config->pch_pfit.pos = (x << 16) | y; in intel_pch_panel_fitting()167 pipe_config->pch_pfit.size = (width << 16) | height; in intel_pch_panel_fitting()168 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; in intel_pch_panel_fitting()
1773 (crtc_state->pch_pfit.enabled || in intel_ddi_enable_transcoder_func()1774 crtc_state->pch_pfit.force_thru)) in intel_ddi_enable_transcoder_func()
861 } pch_pfit; member
4017 if (crtc_state->pch_pfit.enabled) { in skl_pipe_downscale_amount()4019 uint32_t pfit_size = crtc_state->pch_pfit.size; in skl_pipe_downscale_amount()
