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Searched refs:mmUVD_VCPU_CACHE_OFFSET2 (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h90 #define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A macro
Duvd_4_2_d.h64 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
Duvd_5_0_d.h70 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
Duvd_6_0_d.h86 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
Duvd_7_0_offset.h184 #define mmUVD_VCPU_CACHE_OFFSET2 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h346 #define mmUVD_VCPU_CACHE_OFFSET2 macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c569 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); in uvd_v4_2_mc_resume()
Duvd_v5_0.c279 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v5_0_mc_resume()
Duvd_v7_0.c694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); in uvd_v7_0_mc_resume()
833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); in uvd_v7_0_sriov_start()
Duvd_v6_0.c615 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v6_0_mc_resume()
Dvcn_v1_0.c310 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v1_0_mc_resume()