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Searched refs:mmUVD_SUVD_CGC_GATE (Results 1 – 8 of 8) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_d.h89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
Duvd_6_0_d.h105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
Duvd_7_0_offset.h66 #define mmUVD_SUVD_CGC_GATE … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c615 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
653 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
710 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
741 WREG32(mmUVD_SUVD_CGC_GATE, data1);
Duvd_v6_0.c632 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
700 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1264 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1311 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1369 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1402 WREG32(mmUVD_SUVD_CGC_GATE, data1);
Duvd_v7_0.c1583 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1630 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1639 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1672 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
Dvcn_v1_0.c408 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
433 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h132 #define mmUVD_SUVD_CGC_GATE … macro