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Searched refs:mmUVD_RBC_RB_CNTL (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h70 #define mmUVD_RBC_RB_CNTL 0x3DA9 macro
Duvd_4_2_d.h74 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_5_0_d.h80 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_6_0_d.h96 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_7_0_offset.h202 #define mmUVD_RBC_RB_CNTL … macro
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Duvd_v4_2.c351 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_start()
372 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
389 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_stop()
Duvd_v5_0.c403 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
423 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
438 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v5_0_stop()
Duvd_v7_0.c894 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
1065 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); in uvd_v7_0_start()
1087 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, in uvd_v7_0_start()
1122 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v7_0_stop()
Dvcn_v1_0.c739 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start()
761 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start()
807 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); in vcn_v1_0_stop()
Duvd_v6_0.c830 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v6_0_start()
881 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v6_0_stop()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h364 #define mmUVD_RBC_RB_CNTL … macro