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Searched refs:mmSDMA0_CLK_CTRL (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c80 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
111 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
118 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
132 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
146 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
161 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
175 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
1500 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
1510 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
[all …]
Dmxgpu_vi.c93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
224 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
245 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
Dcik_sdma.c903 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
904 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
906 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
909 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
911 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
914 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
Dsdma_v4_0.c62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
121 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
1449 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_update_medium_grain_clock_gating()
1459 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); in sdma_v4_0_update_medium_grain_clock_gating()
1476 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_update_medium_grain_clock_gating()
1487 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); in sdma_v4_0_update_medium_grain_clock_gating()
1593 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
Dsdma_v2_4.c66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
73 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h66 #define mmSDMA0_CLK_CTRL … macro
Dsdma0_4_0_offset.h68 #define mmSDMA0_CLK_CTRL 0x001b macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h160 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_3_0_1_d.h157 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_2_0_d.h222 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_3_0_d.h294 #define mmSDMA0_CLK_CTRL 0x3403 macro