Searched refs:mmMC_SEQ_WR_CTL_D0_LP (Results 1 – 7 of 7) sorted by relevance
1004 #define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F macro
818 #define mmMC_SEQ_WR_CTL_D0_LP 0xa9f macro
922 #define mmMC_SEQ_WR_CTL_D0_LP 0xa9f macro
2423 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in iceland_check_s0_mc_reg_index()2624 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in iceland_initialize_mc_reg_table()
2493 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in ci_check_s0_mc_reg_index()2694 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ… in ci_initialize_mc_reg_table()
2874 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in tonga_check_s0_mc_reg_index()3090 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, in tonga_initialize_mc_reg_table()
4598 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in ci_check_s0_mc_reg_index()4798 WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()