Home
last modified time | relevance | path

Searched refs:mmCP_MEM_SLP_CNTL (Results 1 – 14 of 14) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c92 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
223 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
Dsi.c543 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
640 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
740 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
820 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
897 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
Dgfx_v6_0.c2637 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2640 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2661 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2664 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
Dgfx_v9_0.c3595 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
3598 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
3624 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
3627 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
3851 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_get_clockgating_state()
Dgfx_v8_0.c301 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
464 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
671 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
704 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5766 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5959 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5962 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v7_0.c3640 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3643 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
3693 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3696 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h455 #define mmCP_MEM_SLP_CNTL 0x3079 macro
Dgfx_7_0_d.h255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
Dgfx_7_2_d.h257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
Dgfx_8_0_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
Dgfx_8_1_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
/Linux-v4.19/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2440 #define mmCP_MEM_SLP_CNTL … macro
Dgc_9_1_offset.h2754 #define mmCP_MEM_SLP_CNTL … macro
Dgc_9_2_1_offset.h2692 #define mmCP_MEM_SLP_CNTL … macro