/Linux-v4.19/drivers/gpu/drm/radeon/ |
D | cypress_dpm.c | 956 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); in cypress_populate_mc_reg_addresses() 958 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); in cypress_populate_mc_reg_addresses() 971 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table() 972 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table() 975 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table() 976 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table() 979 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table() 980 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table() 983 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table() 984 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; in cypress_set_mc_reg_address_table() [all …]
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D | btc_dpm.c | 1923 switch (table->mc_reg_address[i].s1) { in btc_set_mc_special_registers() 1926 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in btc_set_mc_special_registers() 1927 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in btc_set_mc_special_registers() 1939 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in btc_set_mc_special_registers() 1940 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in btc_set_mc_special_registers() 1955 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in btc_set_mc_special_registers() 1956 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in btc_set_mc_special_registers() 1983 table->mc_reg_address[i].s0 = in btc_set_s0_mc_reg_index() 1984 btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in btc_set_s0_mc_reg_index() 1985 address : table->mc_reg_address[i].s1; in btc_set_s0_mc_reg_index() [all …]
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D | cypress_dpm.h | 39 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member
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D | si_dpm.h | 117 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member
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D | ni_dpm.h | 57 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member
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D | ni_dpm.c | 2715 switch (table->mc_reg_address[i].s1) { in ni_set_mc_special_registers() 2720 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ni_set_mc_special_registers() 2721 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ni_set_mc_special_registers() 2731 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ni_set_mc_special_registers() 2732 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ni_set_mc_special_registers() 2746 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ni_set_mc_special_registers() 2747 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ni_set_mc_special_registers() 2838 table->mc_reg_address[i].s0 = in ni_set_s0_mc_reg_index() 2839 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ni_set_s0_mc_reg_index() 2840 address : table->mc_reg_address[i].s1; in ni_set_s0_mc_reg_index() [all …]
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D | ci_dpm.h | 86 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
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D | ci_dpm.c | 4344 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers() 4347 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers() 4348 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers() 4358 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers() 4359 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers() 4371 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers() 4372 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers() 4384 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers() 4385 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers() 4499 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index() [all …]
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D | si_dpm.c | 5363 switch (table->mc_reg_address[i].s1 << 2) { in si_set_mc_special_registers() 5366 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in si_set_mc_special_registers() 5367 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in si_set_mc_special_registers() 5377 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in si_set_mc_special_registers() 5378 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in si_set_mc_special_registers() 5391 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers() 5392 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers() 5403 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in si_set_mc_special_registers() 5404 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in si_set_mc_special_registers() 5498 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in si_set_s0_mc_reg_index() [all …]
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D | radeon_mode.h | 668 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member
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D | radeon_atombios.c | 4021 reg_table->mc_reg_address[i].s1 = in radeon_atom_init_mc_reg_table() 4023 reg_table->mc_reg_address[i].pre_reg_data = in radeon_atom_init_mc_reg_table() 4039 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in radeon_atom_init_mc_reg_table() 4043 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in radeon_atom_init_mc_reg_table()
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/Linux-v4.19/drivers/gpu/drm/amd/powerplay/smumgr/ |
D | iceland_smumgr.h | 57 SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
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D | ci_smumgr.h | 58 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
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D | tonga_smumgr.h | 59 SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
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D | iceland_smumgr.c | 1699 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); in iceland_populate_mc_reg_address() 1701 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); in iceland_populate_mc_reg_address() 2468 table->mc_reg_address[i].s0 = in iceland_set_s0_mc_reg_index() 2469 iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) in iceland_set_s0_mc_reg_index() 2470 ? address : table->mc_reg_address[i].s1; in iceland_set_s0_mc_reg_index() 2486 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in iceland_copy_vbios_smc_reg_table() 2515 switch (table->mc_reg_address[i].s1) { in iceland_set_mc_special_registers() 2519 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in iceland_set_mc_special_registers() 2520 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in iceland_set_mc_special_registers() 2531 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in iceland_set_mc_special_registers() [all …]
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D | ci_smumgr.c | 1731 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_address() 1733 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_address() 2538 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index() 2539 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) in ci_set_s0_mc_reg_index() 2540 ? address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index() 2556 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_smc_reg_table() 2585 switch (table->mc_reg_address[i].s1) { in ci_set_mc_special_registers() 2589 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers() 2590 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers() 2601 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers() [all …]
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D | tonga_smumgr.c | 2067 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); in tonga_populate_mc_reg_address() 2069 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); in tonga_populate_mc_reg_address() 2919 table->mc_reg_address[i].s0 = in tonga_set_s0_mc_reg_index() 2920 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, in tonga_set_s0_mc_reg_index() 2923 table->mc_reg_address[i].s1; in tonga_set_s0_mc_reg_index() 2939 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in tonga_copy_vbios_smc_reg_table() 2968 switch (table->mc_reg_address[i].s1) { in tonga_set_mc_special_registers() 2973 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in tonga_set_mc_special_registers() 2974 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in tonga_set_mc_special_registers() 2985 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in tonga_set_mc_special_registers() [all …]
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/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
D | si_dpm.h | 279 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member 625 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member 933 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member
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D | amdgpu_atombios.h | 116 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member
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D | ci_dpm.h | 87 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
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D | ci_dpm.c | 4499 switch(table->mc_reg_address[i].s1) { in ci_set_mc_special_registers() 4502 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers() 4503 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers() 4513 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers() 4514 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; in ci_set_mc_special_registers() 4526 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers() 4527 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers() 4537 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; in ci_set_mc_special_registers() 4538 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; in ci_set_mc_special_registers() 4650 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index() [all …]
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D | si_dpm.c | 5824 switch (table->mc_reg_address[i].s1) { in si_set_mc_special_registers() 5827 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; in si_set_mc_special_registers() 5828 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; in si_set_mc_special_registers() 5838 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; in si_set_mc_special_registers() 5839 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; in si_set_mc_special_registers() 5852 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; in si_set_mc_special_registers() 5853 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; in si_set_mc_special_registers() 5862 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; in si_set_mc_special_registers() 5863 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; in si_set_mc_special_registers() 5954 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in si_set_s0_mc_reg_index() [all …]
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D | amdgpu_atombios.c | 1621 reg_table->mc_reg_address[i].s1 = in amdgpu_atombios_init_mc_reg_table() 1623 reg_table->mc_reg_address[i].pre_reg_data = in amdgpu_atombios_init_mc_reg_table() 1639 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in amdgpu_atombios_init_mc_reg_table() 1643 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in amdgpu_atombios_init_mc_reg_table()
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/Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/ |
D | ppatomctrl.h | 251 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member
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D | ppatomctrl.c | 69 if ((table->mc_reg_address[i].uc_pre_reg_data & in atomctrl_retrieve_ac_timing() 74 } else if ((table->mc_reg_address[i].uc_pre_reg_data & in atomctrl_retrieve_ac_timing() 118 table->mc_reg_address[i].s1 = in atomctrl_set_mc_reg_address_table() 120 table->mc_reg_address[i].uc_pre_reg_data = in atomctrl_set_mc_reg_address_table()
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