Searched refs:max_sh_per_se (Results 1 – 17 of 17) sorted by relevance
1315 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()1449 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()1458 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()1568 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_gpu_init()1585 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_gpu_init()1602 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_gpu_init()[all …]
1631 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()1673 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()1793 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()1801 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()1827 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()3393 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()4335 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()4352 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()4370 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()[all …]
144 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()488 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
347 adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
1796 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1813 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1860 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1876 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1893 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1911 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()3587 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()3638 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()3749 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()3754 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()[all …]
424 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in get_cu_info()
1703 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()1714 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()1718 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()1721 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()1832 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()4885 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
743 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
595 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
809 unsigned max_sh_per_se; member
1432 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
464 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()466 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
3103 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3120 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3138 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3155 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()3172 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()3289 rdev->config.si.max_sh_per_se, in si_gpu_init()3293 rdev->config.si.max_sh_per_se, in si_gpu_init()3298 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()5325 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
3191 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3208 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3226 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3244 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3346 rdev->config.cik.max_sh_per_se, in cik_gpu_init()3351 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()5798 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()6565 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
2136 unsigned max_sh_per_se; member2167 unsigned max_sh_per_se; member
1192 uint8_t max_sh_per_se; member1212 uint8_t max_sh_per_se; member
5653 UCHAR max_sh_per_se; member
