| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 105 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
125 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
195 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
212 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); in dpcd_set_lt_pattern_and_lane_settings()
293 for (lane = 0; lane < src.link_settings.lane_count; lane++) { in update_drive_settings()
347 for (lane = 1; lane < link_training_setting->link_settings.lane_count; in find_max_drive_settings()
405 max_lt_setting->link_settings.lane_count = in find_max_drive_settings()
406 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
411 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
445 (uint32_t)(link_training_setting->link_settings.lane_count); in get_lane_status_and_drive_settings()
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| /Linux-v4.19/drivers/gpu/drm/i915/ |
| D | intel_dp_link_training.c | 45 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
83 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
84 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
110 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
112 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
119 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
149 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
185 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { in intel_dp_link_training_clock_recovery()
295 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
303 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
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| D | intel_dpio_phy.c | 571 bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
573 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
581 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
658 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
671 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
679 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
687 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
710 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
724 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
751 if (crtc->config->lane_count > 2) { in chv_data_lane_soft_reset()
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| D | vlv_dsi.c | 39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
43 8 * 100), lane_count); in txbyteclkhs()
47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1100 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1149 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1151 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1153 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1203 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1205 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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| D | vlv_dsi_pll.c | 42 int lane_count) in dsi_clk_from_pclk() argument
49 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
123 intel_dsi->lane_count); in vlv_dsi_pll_compute()
325 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_dsi_get_pclk()
354 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_dsi_get_pclk()
483 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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| D | icl_dsi.c | 40 intel_dsi->lane_count); in gen11_dsi_program_esc_clk_div()
85 switch (intel_dsi->lane_count) { in gen11_dsi_power_up_lanes()
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| D | intel_dp_mst.c | 45 int lane_count, slots; in intel_dp_mst_compute_config() local
65 lane_count = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_compute_config()
67 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
86 intel_link_compute_m_n(bpp, lane_count, in intel_dp_mst_compute_config()
96 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_dp_mst_compute_config()
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| D | intel_dsi_vbt.c | 525 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in intel_dsi_vbt_init()
566 computed_ddr = (pclk * bpp) / intel_dsi->lane_count; in intel_dsi_vbt_init()
589 bitrate = (pclk * bpp) / intel_dsi->lane_count; in intel_dsi_vbt_init()
607 switch (intel_dsi->lane_count) { in intel_dsi_vbt_init()
752 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); in intel_dsi_vbt_init()
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| D | intel_dp.c | 386 uint8_t lane_count) in intel_dp_link_params_valid() argument
397 if (lane_count == 0 || in intel_dp_link_params_valid()
398 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
405 int link_rate, uint8_t lane_count) in intel_dp_get_link_train_fallback_values() argument
414 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
415 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
417 intel_dp->max_link_lane_count = lane_count >> 1; in intel_dp_get_link_train_fallback_values()
1731 int bpp, clock, lane_count; in intel_dp_compute_link_config_wide() local
1739 for (lane_count = limits->min_lane_count; in intel_dp_compute_link_config_wide()
1740 lane_count <= limits->max_lane_count; in intel_dp_compute_link_config_wide()
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| D | intel_dsi.h | 62 unsigned int lane_count; member
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| D | intel_ddi.c | 1247 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1806 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
1809 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
2290 width = intel_dp->lane_count; in cnl_ddi_vswing_sequence()
2418 width = intel_dp->lane_count; in icl_combo_phy_ddi_vswing_sequence()
2687 crtc_state->lane_count, is_mst); in intel_ddi_pre_enable_dp()
3199 pipe_config->lane_count = 4; in intel_ddi_get_config()
3209 pipe_config->lane_count = in intel_ddi_get_config()
3215 pipe_config->lane_count = in intel_ddi_get_config()
3291 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
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| D | intel_drv.h | 837 uint8_t lane_count; member
1065 uint8_t lane_count; member
1678 int link_rate, uint8_t lane_count,
1681 int link_rate, uint8_t lane_count);
1738 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
1740 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
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| /Linux-v4.19/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 97 link->cur_link_settings.lane_count, in dp_link_settings_read()
104 link->verified_link_cap.lane_count, in dp_link_settings_read()
111 link->reported_link_cap.lane_count, in dp_link_settings_read()
118 link->preferred_link_setting.lane_count, in dp_link_settings_read()
227 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
387 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
388 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
394 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
395 link->cur_link_settings.lane_count; in dp_phy_settings_write()
403 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
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| /Linux-v4.19/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 323 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
325 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
330 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
335 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
339 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
351 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
377 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
382 lane_count); in analogix_dp_link_start()
397 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
402 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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| D | analogix_dp_core.h | 153 u8 lane_count; member
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| /Linux-v4.19/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 264 uint8_t lane_count; member
900 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
913 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
915 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
919 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
923 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
931 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
936 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
993 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1010 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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| D | mdfld_dsi_dpi.c | 470 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
485 val = lane_count; in mdfld_dsi_dpi_controller_init()
506 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
523 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
749 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
773 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
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| D | mdfld_dsi_output.c | 417 config->lane_count = 4; in mdfld_dsi_get_default_config()
419 config->lane_count = 2; in mdfld_dsi_get_default_config()
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| /Linux-v4.19/drivers/gpu/drm/bridge/ |
| D | parade-ps8622.c | 63 u32 lane_count; member
199 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
576 &ps8622->lane_count)) { in ps8622_probe()
577 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
578 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
581 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 482 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
981 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1020 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1099 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1104 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
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| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_link_encoder.c | 449 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
930 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_output()
969 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_mst_output()
1052 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings()
1057 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()
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| /Linux-v4.19/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 61 int lane_count) in drm_dp_channel_eq_ok() argument
71 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
81 int lane_count) in drm_dp_clock_recovery_ok() argument
86 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
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| /Linux-v4.19/include/drm/ |
| D | drm_dp_helper.h | 955 int lane_count);
957 int lane_count);
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| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_dp.c | 207 int lane_count, in amdgpu_atombios_dp_get_adjust_train() argument
214 for (lane = 0; lane < lane_count; lane++) { in amdgpu_atombios_dp_get_adjust_train()
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| /Linux-v4.19/drivers/gpu/drm/amd/display/dc/ |
| D | dc_dp_types.h | 91 enum dc_lane_count lane_count; member
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