Searched refs:clk_div_reg (Results 1 – 1 of 1) sorted by relevance
705 unsigned int clk_div_reg = 0; in sirfsoc_uart_set_termios() local798 clk_div_reg = baudrate_to_regv[ic].reg_val; in sirfsoc_uart_set_termios()802 if (unlikely(clk_div_reg == 0)) in sirfsoc_uart_set_termios()803 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate, in sirfsoc_uart_set_termios()805 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg); in sirfsoc_uart_set_termios()807 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate, in sirfsoc_uart_set_termios()810 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) / in sirfsoc_uart_set_termios()815 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK) in sirfsoc_uart_set_termios()837 len_val |= (((clk_div_reg & 0xc00) >> 10) << in sirfsoc_uart_set_termios()846 len_val |= (((clk_div_reg & 0xf000) >> 12) << in sirfsoc_uart_set_termios()
