| /Linux-v4.19/drivers/isdn/hisax/ |
| D | teleint.c | 22 #define bytein(addr) inb(addr) macro
31 ret = HFC_BUSY & bytein(ale); in readreg()
33 ret = HFC_BUSY & bytein(ale); in readreg()
38 ret = bytein(adr); in readreg()
51 ret = HFC_BUSY & bytein(ale); in readfifo()
53 ret = HFC_BUSY & bytein(ale); in readfifo()
58 data[i] = bytein(adr); in readfifo()
70 ret = HFC_BUSY & bytein(ale); in writereg()
72 ret = HFC_BUSY & bytein(ale); in writereg()
89 ret = HFC_BUSY & bytein(ale); in writefifo()
[all …]
|
| D | avm_a1.c | 26 #define bytein(addr) inb(addr) macro
31 return (bytein(adr + off)); in readreg()
110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { in avm_a1_interrupt()
113 sval = bytein(cs->hw.avm.cfg_reg); in avm_a1_interrupt()
265 val = bytein(cs->hw.avm.cfg_reg); in setup_avm_a1()
268 val = bytein(cs->hw.avm.cfg_reg + 3); in setup_avm_a1()
271 val = bytein(cs->hw.avm.cfg_reg + 2); in setup_avm_a1()
274 val = bytein(cs->hw.avm.cfg_reg); in setup_avm_a1()
|
| D | avm_a1p.c | 57 #define bytein(addr) inb(addr) macro
68 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); in ReadISAC()
102 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); in ReadHSCX()
150 while ((sval = (~bytein(cs->hw.avm.cfg_reg + ASL0_OFFSET) & ASL0_R_IRQPENDING))) { in avm_a1p_interrupt()
242 model = bytein(cs->hw.avm.cfg_reg + MODREG_OFFSET); in setup_avm_a1_pcmcia()
243 vers = bytein(cs->hw.avm.cfg_reg + VERREG_OFFSET); in setup_avm_a1_pcmcia()
|
| D | sportster.c | 24 #define bytein(addr) inb(addr) macro
56 return (bytein(calc_off(cs->hw.spt.isac, offset))); in ReadISAC()
80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); in ReadHSCX()
93 #define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg))
129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ + 1); in sportster_interrupt()
|
| D | teles0.c | 28 #define bytein(addr) inb(addr) macro
300 if ((val = bytein(cs->hw.teles0.cfg_reg + 0)) != 0x51) { in setup_teles0()
306 if ((val = bytein(cs->hw.teles0.cfg_reg + 1)) != 0x93) { in setup_teles0()
312 val = bytein(cs->hw.teles0.cfg_reg + 2); /* 0x1e=without AB in setup_teles0()
|
| D | teles3.c | 26 #define bytein(addr) inb(addr) macro
31 return (bytein(adr + off)); in readreg()
441 if ((val = bytein(cs->hw.teles3.cfg_reg + 0)) != 0x51) { in setup_teles3()
447 if ((val = bytein(cs->hw.teles3.cfg_reg + 1)) != 0x93) { in setup_teles3()
453 val = bytein(cs->hw.teles3.cfg_reg + 2);/* 0x1e=without AB in setup_teles3()
|
| D | netjet.h | 16 #define bytein(addr) inb(addr) macro
|
| D | elsa.c | 45 #define bytein(addr) inb(addr) macro
147 ret = bytein(adr); in readreg()
243 ret = bytein(cs->hw.elsa.itac); in readitac()
259 v = bytein(cs->hw.elsa.cfg); in TimerRun()
372 val = bytein(cs->hw.elsa.cfg + 0x4c); /* PCI IRQ */ in elsa_interrupt_ipac()
764 int pwr = bytein(cs->hw.elsa.ale); in Elsa_card_msg()
869 val = bytein(cs->hw.elsa.cfg); in setup_elsa_isa()
883 val = bytein(cs->hw.elsa.ale) & ELSA_HW_RELEASE; in setup_elsa_isa()
896 val = bytein(cs->hw.elsa.ale) & ELSA_S0_POWER_BAD; in setup_elsa_isa()
|
| D | nj_s.c | 36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1); in netjet_s_interrupt()
55 s0val = bytein(cs->hw.njet.base + NETJET_IRQSTAT0); in netjet_s_interrupt()
|
| D | mic.c | 22 #define bytein(addr) inb(addr) macro
37 ret = bytein(adr); in readreg()
|
| D | netjet.c | 38 ret = bytein(cs->hw.njet.isac + ((offset & 0xf) << 2)); in NETjet_ReadIC()
158 bytein(cs->hw.njet.base + NETJET_DMACTRL), in mode_tiger()
159 bytein(cs->hw.njet.base + NETJET_IRQMASK0), in mode_tiger()
160 bytein(cs->hw.njet.base + NETJET_IRQSTAT0), in mode_tiger()
163 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); in mode_tiger()
959 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); in inittiger()
|
| D | ix1_micro.c | 30 #define bytein(addr) inb(addr) macro
47 ret = bytein(adr); in readreg()
|
| D | saphir.c | 24 #define bytein(addr) inb(addr) macro
39 ret = bytein(adr); in readreg()
|
| D | gazel.c | 42 #define bytein(addr) inb(addr) macro
47 return bytein(adr + off); in readreg()
75 ret = bytein(adr + 4); in readreg_ipac()
|
| D | hfc_sx.c | 56 #define bytein(addr) inb(addr) macro
74 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in reset_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in write_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in read_fifo()
|
| D | niccy.c | 27 #define bytein(addr) inb(addr) macro
51 ret = bytein(adr); in readreg()
|
| D | asuscom.c | 26 #define bytein(addr) inb(addr) macro
49 ret = bytein(adr); in readreg()
|
| D | nj_u.c | 36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & in netjet_u_interrupt()
|
| D | sedlbauer.c | 84 #define bytein(addr) inb(addr) macro
125 ret = bytein(adr); in readreg()
228 return (bytein(cs->hw.sedl.hscx)); in ReadISAR()
|
| D | isurf.c | 23 #define bytein(addr) inb(addr) macro
|
| D | hfc_2bds0.c | 26 #define bytein(addr) inb(addr) macro
44 ret = bytein(cs->hw.hfcD.addr); in ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); in ReadReg()
|
| D | diva.c | 31 #define bytein(addr) inb(addr) macro
87 ret = bytein(adr); in readreg()
298 while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) { in diva_interrupt()
|
| /Linux-v4.19/drivers/isdn/hysdn/ |
| D | boardergo.c | 29 #define bytein(addr) inb(addr) macro
49 if (!(bytein(card->iobase + PCI9050_INTR_REG) & PCI9050_INTR_REG_STAT1)) { in ergo_interrupt()
138 val = bytein(card->iobase + PCI9050_INTR_REG); /* get actual value */ in ergo_stopcard()
357 bytein(card->iobase + PCI9050_INTR_REG) | in ergo_waitpofready()
|
| /Linux-v4.19/drivers/isdn/hardware/mISDN/ |
| D | hfcmulti.c | 659 unsigned char bytein; in cpld_read_reg() local
667 bytein = readpcibridge(hc, 1); in cpld_read_reg()
670 return bytein; in cpld_read_reg()
|
