Searched refs:XGMAC_DMA_CH_TX_CONTROL (Results 1 – 2 of 2) sorted by relevance
67 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()71 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()211 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()213 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()224 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()226 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()367 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()374 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
163 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x))) macro
