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Searched refs:SDMA0_GFX_RB_CNTL (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c346 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
434 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
436 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
437 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v2_4_gfx_resume()
463 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v2_4_gfx_resume()
Dsdma_v3_0.c521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume()
676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume()
694 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v3_0_gfx_resume()
732 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v3_0_gfx_resume()
Dsdma_v4_0.c506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop()
637 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_gfx_resume()
639 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v4_0_gfx_resume()
640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v4_0_gfx_resume()
657 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v4_0_gfx_resume()
719 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v4_0_gfx_resume()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dcik_sdma.c264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
415 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
Dcikd.h1980 #define SDMA0_GFX_RB_CNTL 0xD200 macro