Searched refs:REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 (Results 1 – 2 of 2) sorted by relevance
333 #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04 macro
343 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, in a6xx_rpmh_stop()354 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); in a6xx_gmu_rpmh_init()
