Searched refs:MI_SEMAPHORE_SYNC_BVE (Results 1 – 2 of 2) sorted by relevance
91 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ macro
2097 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, in intel_ring_init_semaphores()
