Searched refs:IMX6QDL_CLK_PLL5_VIDEO_DIV (Results 1 – 3 of 3) sorted by relevance
156 case IMX6QDL_CLK_PLL5_VIDEO_DIV: in ldb_di_sel_by_clock_id()544 …clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_di… in imx6q_clocks_init()858 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); in imx6q_clocks_init()859 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); in imx6q_clocks_init()860 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); in imx6q_clocks_init()861 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); in imx6q_clocks_init()
61 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,62 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
208 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 macro
