Searched refs:I40E_ITR_MASK (Results 1 – 4 of 4) sorted by relevance
17 #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ macro26 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK)
475 (q_vector->rx.target_itr & I40E_ITR_MASK) == in i40e_update_itr()495 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { in i40e_update_itr()504 itr &= I40E_ITR_MASK; in i40e_update_itr()519 itr &= I40E_ITR_MASK; in i40e_update_itr()593 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { in i40e_update_itr()1600 itr &= I40E_ITR_MASK; in i40e_buildreg_itr()
19 #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ macro28 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK)
1089 (q_vector->rx.target_itr & I40E_ITR_MASK) == in i40e_update_itr()1109 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { in i40e_update_itr()1118 itr &= I40E_ITR_MASK; in i40e_update_itr()1133 itr &= I40E_ITR_MASK; in i40e_update_itr()1207 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) { in i40e_update_itr()2477 itr &= I40E_ITR_MASK; in i40e_buildreg_itr()