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Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/include/dt-bindings/clock/
Dmt8173-clk.h128 #define CLK_TOP_AUD_2_SEL 110 macro
Dmt2712-clk.h165 #define CLK_TOP_AUD_2_SEL 126 macro
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mt2712.c803 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
Dclk-mt8173.c589 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
/Linux-v4.19/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi773 <&topckgen CLK_TOP_AUD_2_SEL>;