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/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dxlnx,zynq-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
14 - $ref: "spi-controller.yaml#"
17 - Michal Simek <michal.simek@xilinx.com>
22 const: xlnx,zynq-qspi-1.0
25 maxItems: 1
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Dspi-zynqmp-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 - $ref: "spi-controller.yaml#"
17 const: xlnx,zynqmp-qspi-1.0
23 maxItems: 1
25 clock-names:
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/Linux-v5.15/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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/Linux-v5.15/drivers/spi/
Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
57 * QSPI Configuration Register - Baud rate and slave select
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
127 supports spi-mem interface.
197 this code to manage the per-word or per-transfer accesses to the
218 used by Xilinx Zynq and ZynqMP.
226 Cadence QSPI is a specialized controller for connecting an SPI
227 Flash over 1/2/4-bit wide bus. Enable this option if you have a
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Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
24 #include <linux/spi/spi-mem.h>
26 /* Generic QSPI register offsets */
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
135 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
141 * struct zynqmp_qspi - Defines qspi driver instance
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/Linux-v5.15/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "arm,cortex-a53";
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/Linux-v5.15/
DMAINTAINERS9 -------------------------
11 1. Always *test* your changes, however small, on at least 4 or
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
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