Searched +full:zynq +full:- +full:ddrc +full:- +full:a05 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only3 ---4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>11 - Manish Narani <manish.narani@xilinx.com>12 - Michal Simek <michal.simek@xilinx.com>15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and16 32-bit bus width configurations.18 The Zynq DDR ECC controller has an optional ECC support in half-bus width[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Zynq power management5 * Copyright (C) 2012 - 2014 Xilinx26 * zynq_pm_ioremap() - Create IO mappings50 * zynq_pm_late_init() - Power management init58 ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); in zynq_pm_late_init()60 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); in zynq_pm_late_init()63 * Enable DDRC clock stop feature. The HW takes care of in zynq_pm_late_init()
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.202 /* DDRC Software control register */205 /* DDRC ECC CE & UE poison mask */209 /* DDRC Device config masks */270 * struct ecc_error_info - ECC error log information.290 * struct synps_ecc_status - ECC status information to report.304 * struct synps_edac_priv - DDR memory controller private instance data.336 * struct synps_platform_data - synps platform data structure.352 * zynq_get_error_info - Get the current ECC error info.363 base = priv->baseaddr; in zynq_get_error_info()[all …]
