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Searched +full:versal +full:- +full:fpga (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/fpga/
Dxlnx,versal-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <nava.manne@xilinx.com>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
19 - enum:
20 - xlnx,versal-fpga
23 - compatible
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/Linux-v5.15/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.manne@xilinx.com>
12 description: The zynqmp-firmware node describes the interface to platform
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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/Linux-v5.15/drivers/fpga/
Dversal-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Xilinx, Inc.
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
29 kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL); in versal_fpga_ops_write()
31 return -ENOMEM; in versal_fpga_ops_write()
35 dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr); in versal_fpga_ops_write()
47 struct device *dev = &pdev->dev; in versal_fpga_probe()
51 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in versal_fpga_probe()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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/Linux-v5.15/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
47 in the Intel IXP4xx XScale-based network processor SoC.
58 bool "Renesas R-Car Gen2 Internal PCI controller"
62 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
64 built-in EHCI/OHCI host controller present on each one.
67 bool "Renesas R-Car PCIe host controller"
71 Say Y here if you want PCIe controller support on R-Car SoCs in host
75 bool "Renesas R-Car PCIe endpoint controller"
79 Say Y here if you want PCIe controller support on R-Car SoCs in
104 bool "Xilinx Versal CPM host bridge support"
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/Linux-v5.15/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2021 Xilinx, Inc.
13 #include <linux/arm-smccc.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
26 #include "zynqmp-debug.h"
35 * struct pm_api_feature_data - PM API Feature data
53 * zynqmp_pm_ret_code() - Convert PMU-FW error codes to Linux error codes
65 return -ENOTSUPP; in zynqmp_pm_ret_code()
67 return -EACCES; in zynqmp_pm_ret_code()
69 return -ECANCELED; in zynqmp_pm_ret_code()
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