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/Linux-v5.15/Documentation/devicetree/bindings/timer/
Dcdns,ttc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence TTC - Triple Timer Counter
10 - Michal Simek <michal.simek@xilinx.com>
23 A list of 3 interrupts; one per timer channel.
28 timer-width:
31 Bit width of the timer, necessary if not 16.
34 - compatible
[all …]
Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Timer/PWM Module (TPM) supports input capture, output compare,
18 the counter bus for the others, provided bit width is the same.
22 const: fsl,imx7ulp-tpm
32 - description: SoC TPM ipg clock
[all …]
Dandestech,atcpit100-timer.txt1 Andestech ATCPIT100 timer
2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
7 used as pulse width modulators (PWM) as well as simple timers.
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
[all …]
/Linux-v5.15/drivers/clocksource/
Dtimer-sp804.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/clocksource/timer-sp.c
5 * Copyright (C) 1999 - 2003 ARM Limited
24 #include "timer-sp.h"
26 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
46 .width = 32,
57 .width = 64,
102 return ~readl_relaxed(sched_clkevt->value); in sp804_read()
115 return -EINVAL; in sp804_clocksource_and_sched_clock_init()
119 writel(0, clkevt->ctrl); in sp804_clocksource_and_sched_clock_init()
[all …]
Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
80 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_get()
[all …]
/Linux-v5.15/arch/m68k/include/asm/
DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
[all …]
DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
[all …]
DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
[all …]
/Linux-v5.15/arch/riscv/boot/dts/canaan/
Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dat91-sam9_l9260.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board
7 /dts-v1/;
11 model = "Olimex sam9-l9260";
12 compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9";
15 stdout-path = "serial0:115200n8";
24 clock-frequency = <32768>;
28 clock-frequency = <18432000>;
34 tcb0: timer@fffa0000 {
35 timer@0 {
[all …]
Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
Dat91sam9260ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <18432000>;
36 tcb0: timer@fffa0000 {
37 timer@0 {
38 compatible = "atmel,tcb-timer";
42 timer@2 {
[all …]
Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
41 tcb0: timer@fff7c000 {
42 timer@0 {
[all …]
Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
37 tcb0: timer@f0010000 {
38 timer@0 {
39 compatible = "atmel,tcb-timer";
43 timer@1 {
[all …]
Dpm9g45.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
40 pinctrl_nand_rb: nand-rb-0 {
47 pinctrl_board_mmc: mmc0-board {
54 tcb0: timer@fff7c000 {
55 timer@0 {
[all …]
Dat91-qil_a9260.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board
5 * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
11 compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
33 tcb0: timer@fffa0000 {
34 timer@0 {
35 compatible = "atmel,tcb-timer";
[all …]
Danimeo_ip.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 /dts-v1/;
13 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
26 stdout-path = &usart2;
35 clock-frequency = <32768>;
39 clock-frequency = <18432000>;
45 tcb0: timer@fffa0000 {
46 timer@0 {
[all …]
Dat91-cosino.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-cosino.dtsi - Device Tree file for Cosino core module
5 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
29 clock-frequency = <32768>;
33 clock-frequency = <12000000>;
39 atmel,adc-ts-wires = <4>;
40 atmel,adc-ts-pressure-threshold = <10000>;
49 pinctrl-0 = <&pinctrl_ebi_addr_nand
51 pinctrl-names = "default";
54 nand-controller {
[all …]
Dat91-sama5d3_xplained.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
14 compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
37 …pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd…
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "arm,cortex-a53";
[all …]
/Linux-v5.15/drivers/pwm/
Dpwm-dwc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
39 /* Timer Control Register */
62 return readl(dwc->base + offset); in dwc_pwm_readl()
67 writel(value, dwc->base + offset); in dwc_pwm_writel()
94 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
98 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); in __dwc_pwm_configure_timer()
100 return -ERANGE; in __dwc_pwm_configure_timer()
101 low = tmp - 1; in __dwc_pwm_configure_timer()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
14 - $ref: mmc-controller.yaml#
19 - rockchip,rk3568-dwcmshc
20 - snps,dwcmshc-sdhci
31 - description: core clock
[all …]
/Linux-v5.15/drivers/gpu/drm/gud/
Dgud_pipe.c1 // SPDX-License-Identifier: MIT
42 …* https://lore.kernel.org/dri-devel/CAKb7UvihLX0hgBOP3VBG7O+atwZcUVCPVuBdfmDMpg0NjXe-cQ@mail.gmail…
60 unsigned int x, y, width, height; in gud_xrgb8888_to_r124() local
65 WARN_ON_ONCE(format->char_per_block[0] != 1); in gud_xrgb8888_to_r124()
68 rect->x1 = ALIGN_DOWN(rect->x1, block_width); in gud_xrgb8888_to_r124()
69 width = drm_rect_width(rect); in gud_xrgb8888_to_r124()
71 len = drm_format_info_min_pitch(format, 0, width) * height; in gud_xrgb8888_to_r124()
73 buf = kmalloc(width * height, GFP_KERNEL); in gud_xrgb8888_to_r124()
81 for (x = 0; x < width; x++) { in gud_xrgb8888_to_r124()
83 unsigned int pixshift = (block_width - pixpos - 1) * bits_per_pixel; in gud_xrgb8888_to_r124()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]

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