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/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_fb.c188 unsigned int tiles; in intel_adjust_tile_offset() local
194 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
196 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
197 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
287 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
302 tiles = *x / tile_width; in intel_compute_aligned_offset()
305 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
618 * of 8 stride tiles. in plane_view_dst_stride_tiles()
719 /* Return number of tiles @color_plane needs. */
726 unsigned int tiles; in calc_plane_normal_size() local
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/Linux-v5.15/Documentation/devicetree/bindings/arm/
Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
Darm,vexpress-juno.yaml18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
146 description: When describing tiles consisting of more than one DCC, its
155 the connection between the motherboard and any tiles. Sometimes the
/Linux-v5.15/include/uapi/drm/
Ddrm_fourcc.h446 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
463 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
481 * This is a tiled layout using 4Kb tiles in row-major layout.
482 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
502 * considered to be made up of normal 128Bx32 Y tiles, Thus
517 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
528 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
551 * corresponds to an area of 4x1 tiles in the main surface. The main surface
574 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
586 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
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Dv3d_drm.h98 * execute the tiles that have been set up by the BCL, or a fixed set
99 * of tiles (in the case of RCL-only blits).
Dvc4_drm.h166 /* By default, the kernel gets to choose the order that the tiles are
167 * rendered in. If this is set, then the tiles will be rendered in a
/Linux-v5.15/include/linux/
Dfb.h311 __u32 length; /* number of tiles in the map */
319 __u32 width; /* number of tiles in the x-axis */
320 __u32 height; /* number of tiles in the y-axis */
332 __u32 width; /* number of tiles in the x-axis */
333 __u32 height; /* number of tiles in the y-axis */
339 __u32 width; /* number of tiles in the x-axis */
340 __u32 height; /* number of tiles in the y-axis */
343 __u32 length; /* number of tiles to draw */
360 /* all dimensions from hereon are in terms of tiles */
362 /* move a rectangular region of tiles from one area to another*/
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/Linux-v5.15/Documentation/admin-guide/perf/
Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
/Linux-v5.15/Documentation/userspace-api/media/v4l/
Dpixfmt-reserved.rst254 (codenamed sunxi) platforms, with 32x32 tiles for the luminance plane
255 and 32x64 tiles for the chrominance plane. The data in each tile is
260 of tiles, resulting in 32-aligned resolutions for the luminance plane
/Linux-v5.15/drivers/gpu/ipu-v3/
Dipu-image-convert.c24 * of 4*4 or 16 tiles. A conversion is then carried out for each
31 * of tiles as the output frame:
59 * output image. Tiles are numbered row major from top left to bottom
344 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", in dump_format()
400 * Calculate downsizing coefficients, which are the same for all tiles,
403 * Also determine the number of tiles necessary to guarantee that no tile
459 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", in calc_image_resize_coefficients()
537 * Output tiles must start at a multiple of 8 bytes horizontally and in find_best_seam()
549 * Tiles in the right row / bottom column may not be allowed to in find_best_seam()
662 * Fill in left position and width and for all tiles in an input column, and
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h315 /* Specifies the number of tiles in the x direction
322 /* Specifies the number of tiles in the y direction to
360 * THIN tiles use an 8x8x1 tile size.
361 * THICK tiles use an 8x8x4 tile size.
/Linux-v5.15/arch/arm/include/debug/
Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
/Linux-v5.15/drivers/video/fbdev/
Dgbefb.c688 The GBE hardware uses a tiled memory to screen mapping. Tiles are in gbefb_set_par()
691 tiles on the right and/or bottom of the screen if needed. in gbefb_set_par()
709 Tiles have the advantage that they can be allocated individually in in gbefb_set_par()
715 Tiles are still allocated as independent chunks of 64KB of in gbefb_set_par()
750 /* Tell gbe about the tiles table location */ in gbefb_set_par()
1162 printk(KERN_ERR "gbefb: couldn't allocate tiles table\n"); in gbefb_probe()
1196 /* map framebuffer memory into tiles table */ in gbefb_probe()
/Linux-v5.15/drivers/gpu/drm/
Ddrm_client_modeset.c412 /* if this tile_pass doesn't cover any of the tiles - keep going */ in drm_client_target_preferred()
417 * all tiles left and above in drm_client_target_preferred()
438 * In case of tiled mode if all tiles not present fallback to in drm_client_target_preferred()
440 * After all tiles are present, try to find the tiled mode in drm_client_target_preferred()
443 * tile 0,0 and set to no mode for all other tiles. in drm_client_target_preferred()
701 * In case of tiled modes, if all tiles are not present in drm_client_firmware_config()
/Linux-v5.15/arch/arm/mach-vexpress/
DKconfig25 ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
/Linux-v5.15/Documentation/ABI/testing/
Dsysfs-driver-hid-picolcd41 tiles get changed and it's not appropriate to expect the application
/Linux-v5.15/arch/arm/
DKconfig.debug1325 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
1332 Note that this will only work with standard A-class core tiles,
1344 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
1349 of the tiles using the RS1 memory map, including all new A-class
1350 core tiles, FPGA-based SMMs and software models.
1353 bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
1358 Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
/Linux-v5.15/drivers/staging/media/hantro/
Dhantro_hevc.c174 /* Need to reallocate due to tiles passed via PPS */ in tile_buffer_reallocate()
317 * Maximum number of tiles times width and height (2 bytes each), in hantro_hevc_dec_init()
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Darm,syscon-icst.yaml30 In the core modules and logic tiles, the ICST is a configurable clock fed

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