Searched +full:sp7021 +full:- +full:pctl (Results 1 – 3 of 3) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for Sunplus SP70218 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/reset/sunplus,sp7021-reset.h>11 #include <dt-bindings/pinctrl/sppctl-sp7021.h>12 #include <dt-bindings/gpio/gpio.h>17 compatible = "sunplus,sp7021";18 model = "Sunplus SP7021";22 compatible = "fixed-clock";[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Sunplus SP7021 Pin Controller11 - Dvorkin Dmitry <dvorkin@tibbo.com>12 - Wells Lu <wellslutw@gmail.com>15 The Sunplus SP7021 pin controller is used to control SoC pins. Please16 refer to pinctrl-bindings.txt in this directory for details of the common19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All[all …]
1 // SPDX-License-Identifier: GPL-2.03 * SP7021 Pin Controller Driver.20 #include <linux/pinctrl/pinconf-generic.h>23 #include <dt-bindings/pinctrl/sppctl-sp7021.h>26 #include "../pinctrl-utils.h"40 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_readl()45 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_writel()50 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_readl()56 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_writel()61 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); in sppctl_gpio_oe_readl()[all …]
