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/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-larb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Local Arbiter
11 - Yong Wu <yong.wu@mediatek.com>
19 - enum:
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
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Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
16 MediaTek SMI have two generations of HW architecture, here is the list
21 There's slight differences between the two SMI, for generation 2, the
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
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/Linux-v6.1/drivers/memory/
Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
19 #include <soc/mediatek/smi.h>
20 #include <dt-bindings/memory/mt2701-larb-port.h>
21 #include <dt-bindings/memory/mtk-memory-port.h>
23 /* SMI COMMON */
39 /* SMI LARB */
66 * or non-security.
104 MTK_SMI_GEN2, /* gen2 smi common */
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/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
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Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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/Linux-v6.1/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
33 SMI Common(Smart Multimedia Interface Common)
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/Linux-v6.1/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/media/
Dmediatek-jpeg-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xia Jiang <xia.jiang@mediatek.com>
12 description: |-
18 - items:
19 - enum:
20 - mediatek,mt8173-jpgdec
21 - mediatek,mt2701-jpgdec
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Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
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/Linux-v6.1/drivers/iommu/
Dmtk_iommu_v1.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2016 MediaTek Inc.
14 #include <linux/dma-mapping.h>
29 #include <asm/dma-iommu.h>
30 #include <dt-bindings/memory/mtk-memory-port.h>
31 #include <dt-bindings/memory/mt2701-larb-port.h>
32 #include <soc/mediatek/smi.h>
76 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
123 return component_bind_all(dev, &data->larb_imu); in mtk_iommu_v1_bind()
130 component_unbind_all(dev, &data->larb_imu); in mtk_iommu_v1_unbind()
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Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
17 #include <linux/io-pgtable.h>
32 #include <soc/mediatek/smi.h>
34 #include <dt-bindings/memory/mtk-memory-port.h>
144 ((((pdata)->flags) & (mask)) == (_x))
233 * In the sharing pgtable case, list data->list to the global list like m4ulist.
234 * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
256 return component_bind_all(dev, &data->larb_imu); in mtk_iommu_bind()
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