| /Linux-v5.15/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
43 - const: riscv
44 - const: riscv # Simulator only
54 https://riscv.org/specifications/
57 - riscv,sv32
58 - riscv,sv39
59 - riscv,sv48
60 - riscv,none
62 riscv,isa:
67 https://riscv.org/specifications/
[all …]
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| /Linux-v5.15/arch/riscv/ |
| D | Makefile | 51 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
52 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
53 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
54 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
55 KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
56 KBUILD_AFLAGS += -march=$(riscv-march-y)
93 boot := arch/riscv/boot
100 head-y := arch/riscv/kernel/head.o
102 core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
104 libs-y += arch/riscv/lib/
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| D | Kconfig | 13 config RISCV config
221 source "arch/riscv/Kconfig.socs"
222 source "arch/riscv/Kconfig.erratas"
541 ROM memory will be arch/riscv/boot/xipImage.
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| /Linux-v5.15/arch/riscv/boot/dts/microchip/ |
| D | microchip-mpfs.dtsi | 21 compatible = "sifive,e51", "sifive,rocket0", "riscv";
27 riscv,isa = "rv64imac";
32 compatible = "riscv,cpu-intc";
39 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
51 mmu-type = "riscv,sv39";
53 riscv,isa = "rv64imafdc";
59 compatible = "riscv,cpu-intc";
66 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
78 mmu-type = "riscv,sv39";
80 riscv,isa = "rv64imafdc";
[all …]
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| /Linux-v5.15/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
36 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
53 mmu-type = "riscv,sv39";
55 riscv,isa = "rv64imafdc";
60 compatible = "riscv,cpu-intc";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
77 mmu-type = "riscv,sv39";
79 riscv,isa = "rv64imafdc";
[all …]
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| D | fu740-c000.dtsi | 26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
37 compatible = "riscv,cpu-intc";
42 compatible = "sifive,bullet0", "riscv";
54 mmu-type = "riscv,sv39";
57 riscv,isa = "rv64imafdc";
61 compatible = "riscv,cpu-intc";
66 compatible = "sifive,bullet0", "riscv";
78 mmu-type = "riscv,sv39";
81 riscv,isa = "rv64imafdc";
[all …]
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| /Linux-v5.15/arch/riscv/kernel/ |
| D | cpu.c | 20 if (!of_device_is_compatible(node, "riscv")) { in riscv_of_processor_hartid()
35 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
56 if (of_device_is_compatible(node, "riscv")) in riscv_of_parent_hartid()
76 if (strcmp(mmu_type, "riscv,sv32") != 0) in print_mmu()
79 if (strcmp(mmu_type, "riscv,sv39") != 0 && in print_mmu()
80 strcmp(mmu_type, "riscv,sv48") != 0) in print_mmu()
113 if (!of_property_read_string(node, "riscv,isa", &isa)) in c_show()
118 && strcmp(compat, "riscv")) in c_show()
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| D | cpufeature.c | 88 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_fill_hwcap()
89 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); in riscv_fill_hwcap()
139 pr_info("riscv: ISA extensions %s\n", print_str); in riscv_fill_hwcap()
145 pr_info("riscv: ELF capabilities %s\n", print_str); in riscv_fill_hwcap()
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| /Linux-v5.15/drivers/clocksource/ |
| D | timer-riscv.c | 116 child = of_get_compatible_child(n, "riscv,cpu-intc"); in riscv_timer_init_dt()
138 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", in riscv_timer_init_dt()
147 "riscv-timer", &riscv_clock_event); in riscv_timer_init_dt()
154 "clockevents/riscv/timer:starting", in riscv_timer_init_dt()
157 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_dt()
162 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
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| /Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 67 riscv,cpu-intc node, which has a riscv node as parent.
69 riscv,ndev:
81 - riscv,ndev
99 riscv,ndev = <10>;
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| D | riscv,cpu-intc.txt | 27 - compatible : "riscv,cpu-intc"
45 compatible = "riscv";
49 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
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| /Linux-v5.15/Documentation/translations/zh_CN/riscv/ |
| D | pmu.rst | 3 :Original: Documentation/riscv/pmu.rst
211 * struct riscv_pmu: arch/riscv/include/asm/perf_event.h
225 * struct riscv_hw_events: arch/riscv/include/asm/perf_event.h
233 [1] https://github.com/riscv/riscv-linux/pull/124
235 [2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/f19TmCNP6yA
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| D | patch-acceptance.rst | 5 :Original: Documentation/riscv/patch-acceptance.rst
13 arch/riscv 开发者维护指南
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| D | boot-image-header.rst | 3 :Original: Documentation/riscv/boot-image-header.rst
33 u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
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| /Linux-v5.15/arch/riscv/include/asm/ |
| D | gdb_xml.h | 13 "qXfer:features:read:riscv-64bit-cpu.xml";
19 "<xi:include href=\"riscv-64bit-cpu.xml\"/>"
25 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
65 "qXfer:features:read:riscv-32bit-cpu.xml";
71 "<xi:include href=\"riscv-32bit-cpu.xml\"/>"
77 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
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| D | image.h | 6 #define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
34 * struct riscv_image_header - riscv kernel image header
|
| /Linux-v5.15/drivers/irqchip/ |
| D | irq-riscv-intc.c | 8 #define pr_fmt(fmt) "riscv-intc: " fmt
129 "irqchip/riscv/intc:starting", in riscv_intc_init()
138 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
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| /Linux-v5.15/arch/riscv/boot/dts/canaan/ |
| D | k210.dtsi | 38 compatible = "canaan,k210", "riscv";
40 riscv,isa = "rv64imafdc";
41 mmu-type = "riscv,none";
49 compatible = "riscv,cpu-intc";
54 compatible = "canaan,k210", "riscv";
56 riscv,isa = "rv64imafdc";
57 mmu-type = "riscv,none";
65 compatible = "riscv,cpu-intc";
117 riscv,ndev = <65>;
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| /Linux-v5.15/drivers/firmware/efi/ |
| D | Makefile | 44 riscv-obj-$(CONFIG_EFI) := efi-init.o riscv-runtime.o
45 obj-$(CONFIG_RISCV) += $(riscv-obj-y)
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| /Linux-v5.15/scripts/ |
| D | subarch.include | 13 -e s/riscv.*/riscv/)
|
| /Linux-v5.15/tools/testing/kunit/qemu_configs/ |
| D | riscv.py | 18 QEMU_ARCH = QemuArchParams(linux_arch='riscv',
26 kernel_path='arch/riscv/boot/Image',
|
| /Linux-v5.15/Documentation/riscv/ |
| D | pmu.rst | 228 * struct riscv_pmu: arch/riscv/include/asm/perf_event.h
245 * struct riscv_hw_events: arch/riscv/include/asm/perf_event.h
253 [1] https://github.com/riscv/riscv-linux/pull/124
255 [2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/f19TmCNP6yA
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| /Linux-v5.15/drivers/clk/sifive/ |
| D | fu540-prci.c | 13 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
|
| /Linux-v5.15/Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 3 :Original: :doc:`../../../riscv/patch-acceptance`
6 arch/riscv linee guida alla manutenzione per gli sviluppatori
|
| /Linux-v5.15/scripts/package/ |
| D | buildtar | 128 riscv)
130 if [ -f "${objtree}/arch/riscv/boot/${i}" ] ; then
131 cp -v -- "${objtree}/arch/riscv/boot/${i}" "${tmpdir}/boot/vmlinux-${KERNELRELEASE}"
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