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/Linux-v5.15/drivers/reset/
Dreset-imx7.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * i.MX7 System Reset Controller (SRC) driver
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/reset/imx7-reset.h>
17 #include <dt-bindings/reset/imx8mq-reset.h>
18 #include <dt-bindings/reset/imx8mp-reset.h>
51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()
53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()
54 signal->offset, signal->bit, value); in imx7_reset_update()
92 unsigned long id, bool assert) in imx7_reset_set() argument
[all …]
Dreset-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Broadcom STB generic reset controller for SW_INIT style reset controller
14 #include <linux/reset-controller.h>
46 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); in brcmstb_reset_assert()
57 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); in brcmstb_reset_deassert()
58 /* Maximum reset delay after de-asserting a line and seeing block in brcmstb_reset_deassert()
59 * operation is typically 14us for the worst case, build some slack in brcmstb_reset_deassert()
73 return readl_relaxed(priv->base + off + SW_INIT_STATUS) & in brcmstb_reset_status()
78 .assert = brcmstb_reset_assert,
85 struct device *kdev = &pdev->dev; in brcmstb_reset_probe()
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx6qp-prtwd3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
[all …]
Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&ethernet0_rgmii_pins_a>;
28 pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
29 pinctrl-names = "default", "sleep";
[all …]
Dmeson8b-mxq.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
22 stdout-path = "serial0:115200n8";
30 vcck: regulator-vcck {
31 compatible = "pwm-regulator";
33 regulator-name = "VCCK";
34 regulator-min-microvolt = <860000>;
35 regulator-max-microvolt = <1140000>;
37 pwm-supply = <&vcc_5v>;
[all …]
Dmeson8m2-mxiii-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2";
27 stdout-path = "serial0:115200n8";
35 adc-keys {
36 compatible = "adc-keys";
37 io-channels = <&saradc 0>;
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/Linux-v5.15/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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/Linux-v5.15/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
[all …]
/Linux-v5.15/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-kii-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb-p20x.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
14 compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";
18 compatible = "gpio-leds";
21 default-state = "off";
27 gpio-keys-polled {
[all …]
Dmeson-gxm-q200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxm.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
Dmeson-gxl-s905d-p230.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxl-s905d.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
Dmeson-gxm-mecool-kiii-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-gxm.dtsi"
10 #include "meson-gx-p23x-q20x.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 compatible = "videostrong,gxm-kiii-pro", "amlogic,s912", "amlogic,meson-gxm";
23 adc-keys {
24 compatible = "adc-keys";
25 io-channels = <&saradc 0>;
[all …]
Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
[all …]
Dmeson-gxm-minix-neo-u9h.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxm.dtsi"
9 #include "meson-gx-p23x-q20x.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 compatible = "minix,neo-u9h", "amlogic,s912", "amlogic,meson-gxm";
15 model = "Minix Neo U9-H";
18 compatible = "gpio-leds";
20 led-white {
[all …]
Dmeson-gxm-rbox-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Andreas Färber
5 * Based on nexbox-a1:
14 /dts-v1/;
16 #include "meson-gxm.dtsi"
19 compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
20 model = "R-Box Pro";
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
39 led-blue {
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
[all …]
Dclk-hfpll.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once()
[all …]
/Linux-v5.15/drivers/gpu/drm/msm/hdmi/
Dhdmi_pll_8960.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
27 * configuration into common-clock-framework.
239 msm_writel(data, pll->mmio + reg); in pll_write()
244 return msm_readl(pll->mmio + reg); in pll_read()
249 return platform_get_drvdata(pll->pdev); in pll_get_phy()
261 /* Assert PLL S/W reset */ in hdmi_pll_enable()
266 /* Wait for a short time before de-asserting in hdmi_pll_enable()
269 * to assert and de-assert. in hdmi_pll_enable()
273 /* De-assert PLL S/W reset */ in hdmi_pll_enable()
[all …]
/Linux-v5.15/drivers/staging/fieldbus/anybuss/
Darcx-anybus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arcx Anybus-S Controller driver
23 /* move to <linux/anybuss-controller.h> when taking this out of staging */
24 #include "anybuss-controller.h"
50 static void do_reset(struct controller_priv *cd, u8 rst_bit, bool reset) in do_reset() argument
52 mutex_lock(&cd->ctrl_lock); in do_reset()
54 * CPLD_CONTROL is write-only, so cache its value in in do_reset()
55 * cd->control_reg in do_reset()
57 if (reset) in do_reset()
58 cd->control_reg &= ~rst_bit; in do_reset()
[all …]
/Linux-v5.15/drivers/fpga/
Dice40-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/fpga/fpga-mgr.h>
21 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
22 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
28 struct gpio_desc *reset; member
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
62 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in ice40_fpga_ops_write_init()
[all …]
/Linux-v5.15/drivers/net/mdio/
Dfwnode_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
28 if (err == -ENOENT) in fwnode_find_mii_timestamper()
34 return ERR_PTR(-EINVAL); in fwnode_find_mii_timestamper()
46 if (rc == -EPROBE_DEFER) in fwnode_mdiobus_phy_device_register()
50 phy->irq = rc; in fwnode_mdiobus_phy_device_register()
51 mdio->irq[addr] = rc; in fwnode_mdiobus_phy_device_register()
53 phy->irq = mdio->irq[addr]; in fwnode_mdiobus_phy_device_register()
56 if (fwnode_property_read_bool(child, "broken-turn-around")) in fwnode_mdiobus_phy_device_register()
57 mdio->phy_ignore_ta_mask |= 1 << addr; in fwnode_mdiobus_phy_device_register()
59 fwnode_property_read_u32(child, "reset-assert-us", in fwnode_mdiobus_phy_device_register()
[all …]
/Linux-v5.15/drivers/clk/tegra/
Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
30 /* Handlers for SoC-specific reset lines */
102 * access after disabling clock. Since the reset driver has no in tegra_clk_rst_assert()
103 * knowledge of which reset IDs represent which devices, simply do in tegra_clk_rst_assert()
116 return -EINVAL; in tegra_clk_rst_assert()
130 return -EINVAL; in tegra_clk_rst_deassert()
195 * All non-boot peripherals will be in reset state on resume. in tegra_clk_periph_resume()
196 * Wait for 5us of reset propagation delay before de-asserting in tegra_clk_periph_resume()
[all …]
/Linux-v5.15/sound/arm/
Dpxa2xx-ac97-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
21 #include <sound/pxa2xx-lib.h>
24 #include <mach/regs-ac97.h>
48 int val = -ENODEV; in pxa2xx_ac97_read()
52 return -ENODEV; in pxa2xx_ac97_read()
73 val = -ETIMEDOUT; in pxa2xx_ac97_read()
110 ret = -EIO; in pxa2xx_ac97_write()
129 GCR &= ~GCR_COLD_RST; /* then assert nCRST */ in pxa_ac97_cold_pxa25x()
142 /* warm reset broken on Bulverde, so manually keep AC97 reset high */ in pxa_ac97_warm_pxa27x()
[all …]
/Linux-v5.15/arch/arm/mach-sunxi/
Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
71 /* R_CPUCFG registers, specific to sun8i-a83t */
111 is_compatible = of_device_is_compatible(node, "arm,cortex-a15"); in sunxi_core_is_cortex_a15()
[all …]

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