| /Linux-v5.15/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
23 u8 shift; member
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
[all …]
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| /Linux-v5.15/drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
[all …]
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| /Linux-v5.15/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
18 int shift; member
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
125 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
[all …]
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| D | clk-inverter.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
16 int shift; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
43 pr_err("%s: unsupported phase %d for %s\n", in rockchip_inv_set_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/leds/backlight/ |
| D | sky81452-backlight.txt | 1 SKY81452-backlight bindings
4 - compatible : Must be "skyworks,sky81452-backlight"
7 - name : Name of backlight device. Default is 'lcd-backlight'.
8 - gpios : GPIO to use to EN pin.
10 - led-sources : List of enabled channels from 0 to 5.
12 - skyworks,ignore-pwm : Ignore both PWM input
13 - skyworks,dpwm-mode : Enable DPWM dimming mode, otherwise Analog dimming.
14 - skyworks,phase-shift : Enable phase shift mode
15 - skyworks,short-detection-threshold-volt
17 - skyworks,current-limit-mA
[all …]
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| /Linux-v5.15/drivers/mmc/host/ |
| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
60 #define HIWORD_UPDATE(val, mask, shift) \ argument
61 ((val) << (shift) | (mask) << ((shift) + 16))
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| /Linux-v5.15/drivers/staging/iio/Documentation/ |
| D | sysfs-bus-iio-dds | 4 Contact: linux-iio@vger.kernel.org
8 which allows for pin controlled FSK Frequency Shift Keying
15 Contact: linux-iio@vger.kernel.org
24 Contact: linux-iio@vger.kernel.org
34 Contact: linux-iio@vger.kernel.org
36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
45 Contact: linux-iio@vger.kernel.org
48 the desired value in rad. If shared across all phase registers
[all …]
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| /Linux-v5.15/include/linux/ |
| D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
71 * when an interrupt takes places versus a high speed, fine-grained
94 * https://lists.ntp.org/pipermail/hackers/2008-January/003487.html
[all …]
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| /Linux-v5.15/drivers/gpu/drm/i915/selftests/ |
| D | i915_syncmap.c | 41 for (d = 0; d < depth - 1; d++) { in __sync_print()
42 if (last & BIT(depth - d - 1)) in __sync_print()
47 *sz -= len; in __sync_print()
49 len = scnprintf(buf, *sz, "%x-> ", idx); in __sync_print()
51 *sz -= len; in __sync_print()
55 len = scnprintf(buf, *sz, "0x%016llx", p->prefix << p->height << SHIFT); in __sync_print()
57 *sz -= len; in __sync_print()
58 X = (p->height + SHIFT) / 4; in __sync_print()
59 scnprintf(buf - X, *sz + X, "%*s", X, "XXXXXXXXXXXXXXXXX"); in __sync_print()
61 if (!p->height) { in __sync_print()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_util.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
12 #define REG_MASK(n) ((BIT(n)) - 1)
38 * @ clip: clip shift
44 * @ prec_shift: precision shift
45 * @ adjust_a: A-coefficients for mapping curve
46 * @ adjust_b: B-coefficients for mapping curve
47 * @ adjust_c: C-coefficients for mapping curve
70 * @ init_phase_x: horizontal initial phase
71 * @ phase_step_x: horizontal phase step
[all …]
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| /Linux-v5.15/arch/parisc/include/asm/ |
| D | hash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * HP-PA only implements integer multiply in the FPU. However, for
7 * integer multiplies by constant, it has a number of shift-and-add
8 * (but no shift-and-subtract, sigh!) instructions that a compiler
20 * PA7100 pairing rules. This is an in-order 2-way superscalar processor.
21 * Only one instruction in a pair may be a shift (by more than 3 bits),
22 * but other than that, simple ALU ops (including shift-and-add by up
25 * PA8xxx processors also dual-issue ALU instructions, although with
28 * This 6-step sequence was found by Yevgen Voronenko's implementation
36 * Phase 1: Compute a = (x << 19) + x, in __hash_32()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/clock/ti/ |
| D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
7 (reference clock and bypass clock), with analog phase locked
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
[all …]
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| /Linux-v5.15/kernel/time/ |
| D | ntp.c | 1 // SPDX-License-Identifier: GPL-2.0
49 * phase-lock loop variables
82 /* constant (boot-param configurable) NTP tick adjustment (upscaled) */
91 * The following variables are used when a pulse-per-second (PPS) signal
96 #define PPS_POPCORN 4 /* popcorn spike threshold (shift) */
97 #define PPS_INTMIN 2 /* min freq interval (s) (shift) */
98 #define PPS_INTMAX 8 /* max freq interval (s) (shift) */
105 static long pps_tf[3]; /* phase median filter */
108 static int pps_shift; /* current interval duration (s) (shift) */
122 /* PPS kernel consumer compensates the whole phase error immediately.
[all …]
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| /Linux-v5.15/drivers/regulator/ |
| D | pf8x00-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0+
97 #define PF8X00_SW_BASE(i) (8 * (i - PF8X00_BUCK1) + PF8X00_SW1_CONFIG1)
106 #define PF8X00_LDO_BASE(i) (6 * (i - PF8X00_LDO1) + PF8X00_LDO1_CONFIG1)
202 regmap_update_bits(chip->regmap, reg, in swxilim_select()
211 struct pf8x00_chip *chip = config->driver_data; in handle_ilim_property()
215 if ((desc->id >= PF8X00_BUCK1) && (desc->id <= PF8X00_BUCK7)) { in handle_ilim_property()
216 ret = of_property_read_u32(np, "nxp,ilim-ma", &val); in handle_ilim_property()
218 dev_dbg(chip->dev, "unspecified ilim for BUCK%d, use value stored in OTP\n", in handle_ilim_property()
219 desc->id - PF8X00_LDO4); in handle_ilim_property()
223 dev_warn(chip->dev, "nxp,ilim-ma is deprecated, please use regulator-max-microamp\n"); in handle_ilim_property()
[all …]
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| /Linux-v5.15/arch/x86/crypto/ |
| D | aesni-intel_avx-x86_64.S | 48 ## Vinodh Gopal et. al. Optimized Galois-Counter-Mode Implementation
51 ## Erdinc Ozturk et. al. Enabling High-Performance Galois-Counter-Mode
61 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
63 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
66 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
68 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
82 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
84 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
85 ## | 32-bit Sequence Number (A0) |
86 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/regulator/ |
| D | nxp,pf8x00-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/nxp,pf8x00-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Troy Kisky <troy.kisky@boundarydevices.com>
16 linear and one vsnvs regulators. It has built-in one time programmable
22 - nxp,pf8100
23 - nxp,pf8121a
24 - nxp,pf8200
[all …]
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| /Linux-v5.15/drivers/crypto/vmx/ |
| D | ghashp8-ppc.pl | 2 # SPDX-License-Identifier: GPL-2.0
26 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
27 # faster than "4-bit" integer-only compiler-generated 64-bit code.
30 $flavour=shift;
31 $output =shift;
48 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
49 ( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
50 die "can't locate ppc-xlate.pl";
77 le?vxor 5,5,6 # set a b-endian mask
80 vspltisb $xC2,-16 # 0xf0
[all …]
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| /Linux-v5.15/include/uapi/linux/ |
| D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
82 int shift; /* interval duration (s) (shift) (ro) */ member
121 int shift; /* interval duration (s) (shift) (ro) */ member
152 #define ADJ_OFFSET_SINGLESHOT 0x8001 /* old-fashioned adjtime */
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/mfd/ |
| D | sky81452.txt | 4 - compatible : Must be "skyworks,sky81452"
5 - reg : I2C slave address
8 - backlight : container node for backlight following the binding
9 in leds/backlight/sky81452-backlight.txt
10 - regulator : container node for regulators following the binding
11 in regulator/sky81452-regulator.txt
20 compatible = "skyworks,sky81452-backlight";
21 name = "pwm-backlight";
22 led-sources = <0 1 2 3 6>;
23 skyworks,ignore-pwm;
[all …]
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| /Linux-v5.15/sound/soc/codecs/ |
| D | wm8770.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8770.c -- WM8770 ALSA SoC Audio driver
105 regcache_mark_dirty(wm8770->regmap); \
114 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
115 static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
116 static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
166 SOC_ENUM("DAC1 Phase", dac_phase[0]),
170 SOC_ENUM("DAC2 Phase", dac_phase[1]),
174 SOC_ENUM("DAC3 Phase", dac_phase[2]),
178 SOC_ENUM("DAC4 Phase", dac_phase[3]),
[all …]
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| /Linux-v5.15/arch/microblaze/include/asm/ |
| D | hash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * multiply using shifts and adds. GCC can find a 9-step solution, but
12 * this 6-step solution was found by Yevgen Voronenko's implementation
17 * 6-shift, 6-add sequences for computing x * 0x61C88647. They are all
21 * return (a<<11) + (b<<6) + (c<<3) - b;
37 /* Phase 1: Compute three intermediate values */ in __hash_32()
43 /* Phase 2: Compute (a << 11) + (b << 6) + (c << 3) - b */ in __hash_32()
49 return a - b; /* (a << 11) + (b << 6) + (c << 3) - b */ in __hash_32()
56 * addition-subtraction chain. This one is not known to be in __hash_32()
57 * optimal, but at 37 steps, it's decent for a 31-bit multiplier. in __hash_32()
[all …]
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| /Linux-v5.15/drivers/clk/qcom/ |
| D | clk-alpha-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
59 * struct clk_alpha_pll - phase locked loop (PLL)
80 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
83 * @width: width of post-divider
84 * @post_div_shift: shift to differentiate between odd & even post-divider
85 * @post_div_table: table with PLL odd and even post-divider settings
86 * @num_post_div: Number of PLL post-divider settings
|
