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5 communication between a host and up to four peripherals. This document will13 peripherals on that bus.26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so42 Peripherals with DSI as control bus, or no control bus45 Peripherals with the DSI bus as the primary control bus, or peripherals with48 DSI peripherals, but individual bindings may want to define additional,55 Some DSI peripherals respond to more than a single virtual channel. In that64 Peripherals with a different control bus67 There are peripherals that have I2C/SPI (or some other non-DSI bus) as the69 path). Connections between such peripherals and a DSI host can be represented[all …]
53 traditional PC serial port. The bus supplies power to peripherals54 and allows for hot swapping. Up to 127 USB peripherals can be57 The USB host is the root of the tree, the peripherals are the59 Most PCs now have USB host ports, used to connect peripherals74 After choosing your HCD, then select drivers for the USB peripherals139 port and provide USB compatibility to peripherals designed with
58 want peripherals and CPU frequency scaling to work.74 Say Y if you want peripherals and CPU frequency scaling to work.89 Say Y if you want peripherals and CPU frequency scaling to work.116 devices, aka g12a. Say Y if you want peripherals to work.
35 /* AHB Peripherals */38 /* FAST Peripherals */41 /* SLOW Peripherals */51 * AHB peripherals54 /* AHB Peripherals Bridge Controller */68 * FAST peripherals89 * SLOW peripherals120 * REST peripherals
73 bool "Rely on OTG and EH Targeted Peripherals List"77 product list, so USB peripherals not listed there will be80 "Targeted Peripherals List". "Embedded Hosts" are likewise81 allowed to support only a limited number of peripherals.
18 another: from CPU to SoC peripherals and between some SoC peripherals20 some peripherals). In case of any protocol error, device not responding
3 The NBUS is a bus used to interface with peripherals in the Technologic20 The NBUS node can contain zero or more child nodes representing peripherals
51 /* irq numbers to onboard peripherals */68 * peripherals that live in the nGCS[x] areas, which are quite numerous173 /* physical offset addresses for the peripherals */185 /* some configurations for the peripherals */
11 * peripherals that live in the nGCS[x] areas, which are quite numerous21 /* physical offset addresses for the peripherals */
16 /* irq numbers to onboard peripherals */95 /* physical offset addresses for the peripherals */109 /* some configurations for the peripherals */
101 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */110 /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */120 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */129 /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
3 A device which handles data aquisition from compatible USB based peripherals.6 Note: This device does not expose the peripherals as USB devices.
8 * Lowlevel functions for Advanced Micro Peripherals Ltd AUDIO200017 #define VT1724_SUBDEVICE_AUDIO2000 0x12142417 /* Advanced Micro Peripherals Ltd AUDIO2000 */
6 The auxiliary peripherals (UART, SPI1, and SPI2) have a small register7 area controlling clock gating to the peripherals, and providing an IRQ
19 Definition: base address of CLKDIV peripherals.24 Definition: number of CLKDIV peripherals.
33 /* On chip peripherals */35 /* peripherals that are always instantiated */67 /* On chip peripherals */69 /* peripherals that are always instantiated */
7 title: ARM Primecell Peripherals13 ARM, Ltd. Primecell peripherals have a standard id register that can be used to
14 ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)15 ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
9 /* apb peripherals */42 /* axi peripherals */
11 Plug and Play (PnP) is a standard for peripherals which allows those12 peripherals to be configured by software, e.g. assign IRQ's or other
3 QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips4 that utilize the Qualcomm SPMI implementation. These peripherals provide an
13 The Hi3798CV200 Peripheral Controller controls peripherals, queries14 their status, and configures some functions of peripherals.
4 The CE4100 SoC uses for in core peripherals the following compatible44 This node describes the in-core peripherals. Required property:
33 Peripherals section in Samsung/Meritech SMDK244036 There is no current support for any of the extra peripherals on the
40 * The ColdFire SoC internal peripherals are mapped into virtual address59 * We need to treat built-in peripherals and bus based address ranges60 * differently. Local built-in peripherals (and the ColdFire SoC parts
