Searched +full:mt8173 +full:- +full:u3phy (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: MediaTek T-PHY Controller Device Tree Bindings11 - Chunfeng Yun <chunfeng.yun@mediatek.com>14 The T-PHY controller supports physical layer functionality for a number of17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:19 -----------------------------------67 pattern: "^t-phy@[0-9a-f]+$"[all …]
14 #include <dt-bindings/clock/mt8173-clk.h>15 #include <dt-bindings/interrupt-controller/irq.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>17 #include <dt-bindings/memory/mt8173-larb-port.h>18 #include <dt-bindings/phy/phy.h>19 #include <dt-bindings/power/mt8173-power.h>20 #include <dt-bindings/reset/mt8173-resets.h>21 #include <dt-bindings/gce/mt8173-gce.h>22 #include <dt-bindings/thermal/thermal.h>23 #include "mt8173-pinfunc.h"[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)8 #include <dt-bindings/clock/mt8183-clk.h>9 #include <dt-bindings/gce/mt8183-gce.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/interrupt-controller/irq.h>12 #include <dt-bindings/memory/mt8183-larb-port.h>13 #include <dt-bindings/power/mt8183-power.h>14 #include <dt-bindings/reset-controller/mt8183-resets.h>15 #include <dt-bindings/phy/phy.h>16 #include <dt-bindings/thermal/thermal.h>[all …]
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/clock/mt7622-clk.h>12 #include <dt-bindings/phy/phy.h>13 #include <dt-bindings/power/mt7622-power.h>14 #include <dt-bindings/reset/mt7622-reset.h>15 #include <dt-bindings/thermal/thermal.h>19 interrupt-parent = <&sysirq>;20 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/phy/phy.h>21 /* version V1 sub-banks offset base address */32 /* version V2/V3 sub-banks offset base address */228 /* CDR Charge Pump P-path current adjustment */254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */266 /* I-path capacitance adjustment for Gen1 */302 /* avoid RX sensitivity level degradation only for mt8173 */360 struct u2phy_banks *u2_banks = &instance->u2_banks; in hs_slew_rate_calibrate()361 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate()[all …]
