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Searched +full:latch +full:- +full:ck (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
19 - enum:
20 - mediatek,mt2701-mmc
21 - mediatek,mt2712-mmc
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/Linux-v5.15/drivers/clk/ti/
Dclock.h5 * Tero Kristo (t-kristo@ti.com)
24 s8 latch; member
40 s8 latch; member
95 #define CLK(dev, con, ck) \ argument
101 .clk = ck, \
150 * struct ti_dt_clk - OMAP DT clock alias declarations
/Linux-v5.15/drivers/mmc/host/
Dmtk-sd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
10 #include <linux/dma-mapping.h>
33 #include <linux/mmc/slot-gpio.h>
40 /*--------------------------------------------------------------------------*/
42 /*--------------------------------------------------------------------------*/
49 /*--------------------------------------------------------------------------*/
51 /*--------------------------------------------------------------------------*/
88 /*--------------------------------------------------------------------------*/
90 /*--------------------------------------------------------------------------*/
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/Linux-v5.15/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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/Linux-v5.15/drivers/net/ethernet/intel/e1000e/
Dnetdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
35 static int debug = -1;
109 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
124 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) in __ew32_prepare()
130 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) in __ew32()
133 writel(val, hw->hw_addr + reg); in __ew32()
137 * e1000_regdump - register printout routine
147 switch (reginfo->ofs) { in e1000_regdump()
161 pr_info("%-15s %08x\n", in e1000_regdump()
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