Searched +full:interrupt +full:- +full:controller (Results 1 – 25 of 1104) sorted by relevance
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/pinctrl/samsung.h>
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
24 interrupt-controller;
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| D | exynos5260-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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| D | exynos5420-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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| D | exynos5250-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
24 gpio-controller;
25 #gpio-cells = <2>;
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| /Linux-v5.15/drivers/irqchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
207 bool "J-Core integrated AIC" if COMPILE_TEST
211 Support for the J-Core integrated AIC.
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
229 Enable support for the Renesas Interrupt Controller for external
230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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| /Linux-v5.15/arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
33 gpio-controller;
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| D | exynos5433-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
24 gpio-controller;
25 #gpio-cells = <2>;
27 interrupt-controller;
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| /Linux-v5.15/Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
6 controller in some SoCs, e.g. Hisilicon SD5203.
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
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| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
14 controller, in particular for UARTs
16 - has one 32-bit enable word and one 32-bit status word
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| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
6 - compatible: shall be "marvell,orion-intc"
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
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| D | samsung,exynos4210-combiner.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
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| D | mti,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
21 controller node. This property is inherited, so it may be specified in an
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| D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
14 to all the PRU cores. Most interrupt controllers can route 64 input events
19 remaining 8 (2 through 9) connected to external interrupt controllers
22 The property "ti,irqs-reserved" is used for denoting the connection
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15 source connected to this controller. The value shall be 2.
16 - interrupts: Specifies the list of interrupt lines which are handled by
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| D | samsung,s3c24xx-irq.txt | 1 Samsung S3C24XX Interrupt Controllers
3 The S3C24XX SoCs contain a custom set of interrupt controllers providing a
4 varying number of interrupt sources. The set consists of a main- and sub-
5 controller and on newer SoCs even a second main controller.
8 - compatible: Compatible property value should be "samsung,s3c2410-irq"
9 for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
11 - reg: Physical base address of the controller and length of memory mapped
14 - interrupt-controller : Identifies the node as an interrupt controller
16 - #interrupt-cells : Specifies the number of cells needed to encode an
17 interrupt source. The value shall be 4 and interrupt descriptor shall
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| D | csky,apb-intc.txt | 2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
6 on the apb bus and we only use it as root irq controller.
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
16 Description: Describes APB interrupt controller
20 - compatible
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
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| /Linux-v5.15/Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller
4 controller. It controls the input/output settings on the available pads/pins
6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
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| /Linux-v5.15/Documentation/devicetree/bindings/gpio/ |
| D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
14 module's interrupt.
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
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| D | gpio-mxs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MXS GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
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| D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
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| D | gpio-eic-sprd.txt | 1 Spreadtrum EIC controller bindings
3 The EIC is the abbreviation of external interrupt controller, which can
6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
7 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
10 The EIC-debounce sub-module provides up to 8 source input signal
12 stable status (millisecond resolution) and a single-trigger mechanism
13 is introduced into this sub-module to enhance the input event detection
14 reliability. In addition, this sub-module's clock can be shut off
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
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| /Linux-v5.15/Documentation/devicetree/bindings/pci/ |
| D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
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| /Linux-v5.15/Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 1 Qualcomm SPMI Controller (PMIC Arbiter)
4 controller with wrapping arbitration logic to allow for multiple on-chip
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
11 controller binding requirements for child nodes.
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
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