| /Linux-v5.15/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
82 u32 delay; in rockchip_mmc_set_phase() local
98 return -EINVAL; in rockchip_mmc_set_phase()
105 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
113 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
115 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
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| /Linux-v5.15/drivers/clk/mmp/ |
| D | clk-apbc.c | 15 #include <linux/delay.h>
30 unsigned int delay; member
45 if (apbc->lock) in clk_apbc_prepare()
46 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
48 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
49 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
52 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
54 if (apbc->lock) in clk_apbc_prepare()
55 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
57 udelay(apbc->delay); in clk_apbc_prepare()
[all …]
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| D | clk-gate.c | 12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
[all …]
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| D | clk-apmu.c | 15 #include <linux/delay.h>
35 if (apmu->lock) in clk_apmu_enable()
36 spin_lock_irqsave(apmu->lock, flags); in clk_apmu_enable()
38 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
39 writel_relaxed(data, apmu->base); in clk_apmu_enable()
41 if (apmu->lock) in clk_apmu_enable()
42 spin_unlock_irqrestore(apmu->lock, flags); in clk_apmu_enable()
53 if (apmu->lock) in clk_apmu_disable()
54 spin_lock_irqsave(apmu->lock, flags); in clk_apmu_disable()
56 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; in clk_apmu_disable()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/display/panel/ |
| D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
[all …]
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| /Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
[all …]
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| /Linux-v5.15/drivers/clk/sunxi/ |
| D | clk-mod0.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
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| /Linux-v5.15/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
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| /Linux-v5.15/drivers/clk/ |
| D | clk-palmas.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
13 #include <linux/clk-provider.h>
31 int delay; member
58 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
59 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
61 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
63 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
64 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
[all …]
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| /Linux-v5.15/arch/arm/mach-pxa/ |
| D | mp900.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mp900.c
7 * Based on mach-pxa/gumstix.c
13 #include <linux/init.h>
19 #include <asm/mach-types.h>
25 static void isp116x_pfm_delay(struct device *dev, int delay) in isp116x_pfm_delay() argument
30 int cyc = delay / 10; in isp116x_pfm_delay()
43 .delay = isp116x_pfm_delay,
66 .id = -1,
70 .name = "isp116x-hcd",
[all …]
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| /Linux-v5.15/drivers/media/test-drivers/vidtv/ |
| D | vidtv_tuner.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
20 * struct vidtv_tuner_config - Configuration used to init the tuner.
22 * @mock_power_up_delay_msec: Simulate a power-up delay.
23 * @mock_tune_delay_msec: Simulate a tune delay.
24 * @vidtv_valid_dvb_t_freqs: The valid DVB-T frequencies to simulate.
25 * @vidtv_valid_dvb_c_freqs: The valid DVB-C frequencies to simulate.
26 * @vidtv_valid_dvb_s_freqs: The valid DVB-S frequencies to simulate.
30 * The configuration used to init the tuner module, usually filled
|
| /Linux-v5.15/drivers/media/i2c/ |
| D | bt819.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
[all …]
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| /Linux-v5.15/drivers/clk/actions/ |
| D | owl-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 // Author: David Liu <liuwei@actions-semi.com>
14 #include "owl-common.h"
32 u8 delay; member
51 .delay = _delay, \
63 .hw.init = CLK_HW_INIT(_name, \
78 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
93 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
99 #define mul_mask(m) ((1 << ((m)->width)) - 1)
|
| /Linux-v5.15/arch/arm/lib/ |
| D | delay.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Delay loops based on the OpenRISC implementation.
11 #include <linux/delay.h>
12 #include <linux/init.h>
18 * Default to the loop-based delay implementation.
21 .delay = __loop_delay,
33 return -ENXIO; in read_current_timer()
35 *timer_val = delay_timer->read_current_timer(); in read_current_timer()
49 while ((get_cycles() - start) < cycles) in __timer_delay()
70 clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq, in register_current_timer_delay()
[all …]
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| /Linux-v5.15/init/ |
| D | calibrate.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* calibrate.c: default delay calibration
4 * Excised from init/main.c
9 #include <linux/delay.h>
10 #include <linux/init.h>
28 * loops per jiffy directly, instead of guessing it using delay().
29 * Also, this code tries to handle non-maskable asynchronous events
44 int max = -1; /* index of measured_times with max/min values or not set */ in calibrate_delay_direct()
45 int min = -1; in calibrate_delay_direct()
60 * 1. pre_start <- When we are sure that jiffy switch hasn't happened in calibrate_delay_direct()
[all …]
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| /Linux-v5.15/kernel/locking/ |
| D | locktorture.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Module-based torture test facility for locking
28 #include <linux/delay.h>
36 torture_param(int, nwriters_stress, -1,
37 "Number of write-locking stress-test threads");
38 torture_param(int, nreaders_stress, -1,
39 "Number of read-locking stress-test threads");
77 void (*init)(void); member
117 /* We want a long delay occasionally to force massive contention. */ in torture_lock_busted_write_delay()
160 /* We want a short delay mostly to emulate likely code, and in torture_spin_lock_write_delay()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/bus/ |
| D | ti-sysc.txt | 20 - compatible shall be one of the following generic types:
23 "ti,sysc-omap2"
24 "ti,sysc-omap4"
25 "ti,sysc-omap4-simple"
30 "ti,sysc-omap2-timer"
31 "ti,sysc-omap4-timer"
32 "ti,sysc-omap3430-sr"
33 "ti,sysc-omap3630-sr"
34 "ti,sysc-omap4-sr"
35 "ti,sysc-omap3-sham"
[all …]
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| /Linux-v5.15/arch/parisc/lib/ |
| D | delay.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Precise Delay Loops for parisc
17 #include <linux/init.h>
19 #include <asm/delay.h>
23 /* CR16 based delay: */
40 if ((now - bclock) >= loops) in __cr16_delay()
51 * since CR16's are per-cpu we need to calculate in __cr16_delay()
52 * that. The delay must guarantee that we wait "at in __cr16_delay()
59 loops -= (now - bclock); in __cr16_delay()
|
| /Linux-v5.15/drivers/hwmon/pmbus/ |
| D | max15301.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * extensive empirical testing has revealed that auto-detection of
9 * limit-registers will fail in a random fashion unless the delay
10 * parameter is set to above about 80us. The default delay is set
16 #include <linux/init.h>
21 #include <linux/delay.h>
35 int delay; /* Delay between chip accesses in us */ member
43 static ushort delay = MAX15301_WAIT_TIME; variable
44 module_param(delay, ushort, 0644);
45 MODULE_PARM_DESC(delay, "Delay between chip accesses in us");
[all …]
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| /Linux-v5.15/arch/x86/include/asm/ |
| D | i8259.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h>
33 /* the PIC may need a careful delay on some platforms, hence specific calls */
39 * delay for some accesses to PIC on motherboard or in chipset in inb_pic()
51 * delay for some accesses to PIC on motherboard or in chipset in outb_pic()
66 void (*init)(int auto_eoi); member
82 return legacy_pic->nr_legacy_irqs; in nr_legacy_irqs()
|
| /Linux-v5.15/Documentation/fb/ |
| D | deferred_io.rst | 5 Deferred IO is a way to delay and repurpose IO. It uses host memory as a
10 - userspace app like Xfbdev mmaps framebuffer
11 - deferred IO and driver sets up fault and page_mkwrite handlers
12 - userspace app tries to write to mmaped vaddress
13 - we get pagefault and reach fault handler
14 - fault handler finds and returns physical page
15 - we get page_mkwrite where we add this page to a list
16 - schedule a workqueue task to be run after a delay
17 - app continues writing to that page with no additional cost. this is
19 - the workqueue task comes in and mkcleans the pages on the list, then
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/sound/ |
| D | rt5514.txt | 7 - compatible : "realtek,rt5514".
9 - reg : the I2C address of the device for I2C, the chip select
14 - clocks: The phandle of the master clock to the CODEC
15 - clock-names: Should be "mclk"
17 - interrupts: The interrupt number to the cpu. The interrupt specifier format
20 - realtek,dmic-init-delay-ms
21 Set the DMIC initial delay (ms) to wait it ready for I2C.
|
| /Linux-v5.15/drivers/clk/mediatek/ |
| D | clk-apmixed.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/delay.h>
11 #include "clk-mtk.h"
33 return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK; in mtk_ref2usb_tx_is_prepared()
41 val = readl(tx->base_addr); in mtk_ref2usb_tx_prepare()
44 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
48 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
51 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
61 val = readl(tx->base_addr); in mtk_ref2usb_tx_unprepare()
63 writel(val, tx->base_addr); in mtk_ref2usb_tx_unprepare()
[all …]
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| /Linux-v5.15/arch/arm/kernel/ |
| D | arch_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/init.h>
12 #include <asm/delay.h>
26 /* Use the architected timer for the delay loop. */ in arch_timer_delay_timer_register()
37 return -ENXIO; in arch_timer_arch_init()
|
| /Linux-v5.15/drivers/clk/mxs/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
7 #include <linux/delay.h>
14 * struct clk_pll - mxs pll clock
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
63 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
71 return pll->rate; in clk_pll_recalc_rate()
87 struct clk_init_data init; in mxs_clk_pll() local
[all …]
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