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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt1 * Samsung Exynos5433 CMU (Clock Management Units)
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
Dactions,owl-cmu.txt1 * Actions Semi Owl Clock Management Unit (CMU)
10 "actions,s900-cmu"
11 "actions,s700-cmu"
12 "actions,s500-cmu"
23 dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
24 actions,s500-cmu.h header and can be used in device tree sources.
31 Actions Semi S900 CMU also requires one more clock:
36 cmu: clock-controller@e0160000 {
37 compatible = "actions,s900-cmu";
51 clocks = <&cmu CLK_UART5>;
Dsamsung,exynos-clock.yaml23 - samsung,exynos3250-cmu
24 - samsung,exynos3250-cmu-dmc
25 - samsung,exynos3250-cmu-isp
Defm32-clock.txt4 - compatible: Should be "efm32gg,cmu"
6 - interrupts: Interrupt used by the CMU
/Linux-v5.15/arch/arm/boot/dts/
Dexynos3250.dtsi69 clocks = <&cmu CLK_ARM_CLK>;
92 clocks = <&cmu CLK_ARM_CLK>;
179 clocks = <&cmu CLK_FIN_PLL>;
224 cmu: clock-controller@10030000 { label
225 compatible = "samsung,exynos3250-cmu";
228 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
229 <&cmu CLK_MOUT_ACLK_266_SUB>;
230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 <&cmu CLK_FIN_PLL>;
235 compatible = "samsung,exynos3250-cmu-dmc";
[all …]
Dowl-s500.dtsi8 #include <dt-bindings/clock/actions,s500-cmu.h>
136 clocks = <&cmu CLK_UART0>;
144 clocks = <&cmu CLK_UART1>;
152 clocks = <&cmu CLK_UART2>;
160 clocks = <&cmu CLK_UART3>;
168 clocks = <&cmu CLK_UART4>;
176 clocks = <&cmu CLK_UART5>;
184 clocks = <&cmu CLK_UART6>;
188 cmu: clock-controller@b0160000 { label
189 compatible = "actions,s500-cmu";
[all …]
Dexynos3250-artik5-eval.dts45 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
46 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
47 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
48 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
49 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
50 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
Dexynos3250-artik5.dtsi54 assigned-clocks = <&cmu CLK_SCLK_TSADC>;
58 &cmu {
398 clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
404 assigned-clocks = <&cmu CLK_SCLK_UART0>;
/Linux-v5.15/arch/arm64/boot/dts/actions/
Ds900.dtsi6 #include <dt-bindings/clock/actions,s900-cmu.h>
125 clocks = <&cmu CLK_UART0>;
133 clocks = <&cmu CLK_UART1>;
141 clocks = <&cmu CLK_UART2>;
149 clocks = <&cmu CLK_UART3>;
157 clocks = <&cmu CLK_UART4>;
165 clocks = <&cmu CLK_UART5>;
173 clocks = <&cmu CLK_UART6>;
184 cmu: clock-controller@e0160000 { label
185 compatible = "actions,s900-cmu";
[all …]
Ds700.dtsi6 #include <dt-bindings/clock/actions,s700-cmu.h>
119 clocks = <&cmu CLK_UART0>;
127 clocks = <&cmu CLK_UART1>;
135 clocks = <&cmu CLK_UART2>;
143 clocks = <&cmu CLK_UART3>;
151 clocks = <&cmu CLK_UART4>;
159 clocks = <&cmu CLK_UART5>;
167 clocks = <&cmu CLK_UART6>;
172 cmu: clock-controller@e0168000 { label
173 compatible = "actions,s700-cmu";
[all …]
/Linux-v5.15/drivers/clk/samsung/
Dclk.c343 * for each CMU. It also add CMU register list to register cache.
347 const struct samsung_cmu_info *cmu) in samsung_cmu_register_one() argument
358 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); in samsung_cmu_register_one()
360 if (cmu->pll_clks) in samsung_cmu_register_one()
361 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, in samsung_cmu_register_one()
363 if (cmu->mux_clks) in samsung_cmu_register_one()
364 samsung_clk_register_mux(ctx, cmu->mux_clks, in samsung_cmu_register_one()
365 cmu->nr_mux_clks); in samsung_cmu_register_one()
366 if (cmu->div_clks) in samsung_cmu_register_one()
367 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks); in samsung_cmu_register_one()
[all …]
Dclk-exynos5-subcmu.c17 static const struct exynos5_subcmu_info **cmu; variable
48 * Pass the needed clock provider context and register sub-CMU clocks
62 cmu = _cmu; in exynos5_subcmus_init()
166 if (strcmp(cmu[i]->pd_name, name) == 0) in exynos5_clk_probe()
168 cmu[i], np); in exynos5_clk_probe()
Dclk-exynos5-subcmu.h24 const struct exynos5_subcmu_info **cmu);
/Linux-v5.15/Documentation/devicetree/bindings/net/
Dactions,owl-emac.yaml68 #include <dt-bindings/clock/actions,s500-cmu.h>
76 clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
78 resets = <&cmu RESET_ETHERNET>;
/Linux-v5.15/include/dt-bindings/clock/
Dexynos3250.h22 * Main CMU
260 * Total number of clocks of main CMU.
266 * CMU DMC
287 * Total number of clocks of main CMU.
293 * CMU ISP
/Linux-v5.15/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt240 clocks = <&cmu CLK_DIV_GDL>;
248 clocks = <&cmu CLK_DIV_GDR>;
256 clocks = <&cmu CLK_DIV_ACLK_160>;
264 clocks = <&cmu CLK_DIV_ACLK_200>;
272 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
280 clocks = <&cmu CLK_DIV_ACLK_266>;
288 clocks = <&cmu CLK_DIV_ACLK_100>;
296 clocks = <&cmu CLK_SCLK_MFC>;
/Linux-v5.15/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi373 compatible = "samsung,exynos5433-cmu-top";
388 compatible = "samsung,exynos5433-cmu-cpif";
397 compatible = "samsung,exynos5433-cmu-mif";
408 compatible = "samsung,exynos5433-cmu-peric";
414 compatible = "samsung,exynos5433-cmu-peris";
420 compatible = "samsung,exynos5433-cmu-fsys";
447 compatible = "samsung,exynos5433-cmu-g2d";
461 compatible = "samsung,exynos5433-cmu-disp";
487 compatible = "samsung,exynos5433-cmu-aud";
496 compatible = "samsung,exynos5433-cmu-bus0";
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dowl-mmc.yaml60 clocks = <&cmu 56>;
61 resets = <&cmu 23>;
/Linux-v5.15/Documentation/devicetree/bindings/i2c/
Di2c-owl.yaml52 #include <dt-bindings/clock/actions,s900-cmu.h>
58 clocks = <&cmu CLK_I2C0>;
/Linux-v5.15/arch/powerpc/platforms/44x/
Dfsp2.c32 #define FSP2_CMU_ERR "ibm,cmu-error-irq"
132 pr_err("CMU Error\n"); in cmu_err_handler()
134 panic("CMU Error\n"); in cmu_err_handler()
258 * recorded in the CMU FIR and leading to erroneous interrupt requests in fsp2_probe()
259 * once the CMU interrupt is unmasked. in fsp2_probe()
/Linux-v5.15/fs/coda/
Dcache.c8 * to the Coda project http://www.coda.cs.cmu.edu/ <coda@cs.cmu.edu>.
/Linux-v5.15/Documentation/devicetree/bindings/iio/adc/
Dsamsung,exynos-adc.yaml157 clocks = <&cmu CLK_TSADC>,
158 <&cmu CLK_SCLK_TSADC>;
/Linux-v5.15/drivers/phy/
Dphy-xgene.c10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
[all …]
/Linux-v5.15/arch/mips/vr41xx/common/
DMakefile6 obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
Dcmu.c3 * cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
226 if (request_mem_region(start, size, "CMU") == NULL) in vr41xx_cmu_init()

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