| /Linux-v6.1/drivers/mmc/host/ |
| D | dw_mmc-exynos.c | 92 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; in dw_mci_exynos_get_ciu_div()
143 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
148 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
150 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
152 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
157 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
159 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
168 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
207 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
217 u32 clksel; in dw_mci_exynos_resume_noirq() local
[all …]
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| D | dw_mmc-exynos.h | 19 /* CLKSEL register defines */
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| /Linux-v6.1/Documentation/devicetree/bindings/clock/ti/ |
| D | ti,clksel.yaml | 4 $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
7 title: Binding for TI clksel clock
13 The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
18 const: ti,clksel
22 description: The CLKSEL register range
34 description: The CLKSEL register and bit offset
47 compatible = "ti,clksel";
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| /Linux-v6.1/drivers/clk/ |
| D | clk-milbeaut.c | 17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) macro
254 {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
260 {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
262 {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
[all …]
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| D | clk-qoriq.c | 59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
852 u32 clksel; in mux_set_parent() local
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
866 u32 clksel; in mux_get_parent() local
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
873 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
899 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
902 pll = hwc->info->clksel[idx].pll; in get_pll_div()
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | omap36xx-omap3430es2plus-clocks.dtsi | 9 compatible = "ti,clksel";
24 compatible = "ti,clksel";
54 compatible = "ti,clksel";
85 compatible = "ti,clksel";
172 compatible = "ti,clksel";
194 compatible = "ti,clksel";
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| D | omap34xx-omap36xx-clocks.dtsi | 17 compatible = "ti,clksel";
65 compatible = "ti,clksel";
105 compatible = "ti,clksel";
160 compatible = "ti,clksel";
228 compatible = "ti,clksel";
252 compatible = "ti,clksel";
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| D | omap3430es1-clocks.dtsi | 50 compatible = "ti,clksel";
81 compatible = "ti,clksel";
121 compatible = "ti,clksel";
174 compatible = "ti,clksel";
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| D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 138 compatible = "ti,clksel";
153 compatible = "ti,clksel";
168 compatible = "ti,clksel";
183 compatible = "ti,clksel";
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| D | omap3xxx-clocks.dtsi | 83 compatible = "ti,clksel";
120 compatible = "ti,clksel";
259 compatible = "ti,clksel";
429 compatible = "ti,clksel";
471 compatible = "ti,clksel";
603 compatible = "ti,clksel";
666 compatible = "ti,clksel";
709 compatible = "ti,clksel";
734 compatible = "ti,clksel";
914 compatible = "ti,clksel";
[all …]
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| D | am35xx-clocks.dtsi | 66 compatible = "ti,clksel";
101 compatible = "ti,clksel";
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| D | am33xx-clocks.dtsi | 108 compatible = "ti,clksel";
566 compatible = "ti,clksel";
571 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
589 compatible = "ti,clksel";
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| D | omap36xx-clocks.dtsi | 62 compatible = "ti,clksel";
|
| /Linux-v6.1/drivers/clocksource/ |
| D | timer-cadence-ttc.c | 475 int clksel, ret; in ttc_timer_probe() local
503 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
504 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
505 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
511 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
512 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
513 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
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| /Linux-v6.1/arch/mips/ralink/ |
| D | rt3883.c | 24 u32 clksel; in ralink_clk_init() local
28 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & in ralink_clk_init()
32 switch (clksel) { in ralink_clk_init()
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| /Linux-v6.1/drivers/clk/rockchip/ |
| D | clk-cpu.c | 105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
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| /Linux-v6.1/arch/arm/mach-imx/ |
| D | mach-imx6q.c | 85 u32 clksel; in imx6q_1588_init() local
110 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
117 clksel); in imx6q_1588_init()
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| /Linux-v6.1/drivers/mfd/ |
| D | asic3.c | 387 unsigned long clksel = 0; in asic3_irq_probe() local
397 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
399 clksel); in asic3_irq_probe()
952 unsigned long clksel; in asic3_probe() local
981 clksel = 0; in asic3_probe()
982 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
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| /Linux-v6.1/drivers/gpu/drm/rcar-du/ |
| D | rcar_lvds.c | 130 u32 clksel; member
135 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
243 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
277 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in __rcar_lvds_pll_setup_d3_e3()
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| /Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt76x0/ |
| D | phy.h | 71 u8 pllR28_b3b2; /* clksel option */
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| /Linux-v6.1/Documentation/devicetree/bindings/iio/adc/ |
| D | ti,ads131e08.yaml | 36 Note: clock source is selected using CLKSEL pin.
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| /Linux-v6.1/drivers/pwm/ |
| D | pwm-imx1.c | 83 * both the prescaler (/1 .. /128) and then by CLKSEL in pwm_imx1_config()
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| /Linux-v6.1/drivers/clk/ti/ |
| D | mux.c | 29 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges in ti_clk_mux_get_parent()
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| /Linux-v6.1/sound/soc/codecs/ |
| D | wm8983.h | 247 #define WM8983_CLKSEL 0x0100 /* CLKSEL */
248 #define WM8983_CLKSEL_MASK 0x0100 /* CLKSEL */
249 #define WM8983_CLKSEL_SHIFT 8 /* CLKSEL */
250 #define WM8983_CLKSEL_WIDTH 1 /* CLKSEL */
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| D | wm8985.h | 242 #define WM8985_CLKSEL 0x0100 /* CLKSEL */
243 #define WM8985_CLKSEL_MASK 0x0100 /* CLKSEL */
244 #define WM8985_CLKSEL_SHIFT 8 /* CLKSEL */
245 #define WM8985_CLKSEL_WIDTH 1 /* CLKSEL */
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