| /Linux-v6.1/include/linux/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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| /Linux-v6.1/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
19 'struct clk'.
30 clk, useful across many platforms, as well as an
31 implementation of the clock API in include/linux/clk.h.
32 Architectures utilizing the common struct clk should select
44 source "drivers/clk/versatile/Kconfig"
60 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
89 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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| /Linux-v6.1/drivers/clk/ux500/ |
| D | clk-prcmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
9 #include <linux/clk-provider.h>
10 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
28 u8 source; member
36 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_prepare() local
38 return prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
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| D | u8500_of_clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
14 #include "clk.h"
16 #include "reset-prcc.h"
18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
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| /Linux-v6.1/drivers/cpufreq/ |
| D | spear-cpufreq.c | 2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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| D | tegra124-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
21 struct clk *cpu_clk;
22 struct clk *pllp_clk;
23 struct clk *pllx_clk;
24 struct clk *dfll_clk;
30 struct clk *orig_parent; in tegra124_cpu_switch_to_dfll()
33 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk)); in tegra124_cpu_switch_to_dfll()
37 orig_parent = clk_get_parent(priv->cpu_clk); in tegra124_cpu_switch_to_dfll()
38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
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| /Linux-v6.1/drivers/clk/tegra/ |
| D | clk-super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
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| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
14 #include <linux/clk/tegra.h>
27 #include "clk.h"
49 * clock source as the current parent, we must first change to a backup
50 * timing that has a different clock source.
68 struct clk *parent;
75 struct clk *prev_parent;
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| /Linux-v6.1/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1751-xm019-dc5.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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| /Linux-v6.1/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
21 #include <linux/clk.h>
38 { .compatible = "fsl,mpc5200-cdm", },
55 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
66 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
76 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
82 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
86 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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| /Linux-v6.1/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
41 uint32_t source : 8; /* source index + 1 (0 == none) */ member
50 /* For fixed-factor ones */
68 .source = 1 + R9A06G032_##_src, .name = _n, \
72 .source = 1 + R9A06G032_##_src, .name = _n, \
79 .source = 1 + R9A06G032_##_src, .name = _n, \
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| /Linux-v6.1/drivers/clocksource/ |
| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is disabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | fsl,sai.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - enum:
22 - fsl,vf610-sai
23 - fsl,imx6sx-sai
24 - fsl,imx6ul-sai
25 - fsl,imx7ulp-sai
26 - fsl,imx8mq-sai
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| D | realtek,rt5682s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Derek Fang <derek.fang@realtek.com>
13 Rt5682s(ALC5682I-VS) is a rt5682i variant which supports I2C only.
27 realtek,dmic1-data-pin:
30 - 0 # dmic1 data is not used
31 - 1 # using GPIO2 pin as dmic1 data pin
32 - 2 # using GPIO5 pin as dmic1 data pin
36 realtek,dmic1-clk-pin:
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| /Linux-v6.1/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
105 * struct sdhci_s3c - S3C SDHCI instance
115 * @no_divider: No or non-standard internal clock divider.
125 struct clk *clk_io;
126 struct clk *clk_bus[MAX_BUS_CLK];
133 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
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| /Linux-v6.1/sound/soc/sunxi/ |
| D | sun8i-codec.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (C) Copyright 2010-2016
9 * Mylène Josserand <mylene.josserand@free-electrons.com>
14 #include <linux/clk.h>
23 #include <sound/soc-dapm.h>
186 struct clk *clk_module;
200 regcache_cache_only(scodec->regmap, false); in sun8i_codec_runtime_resume()
202 ret = regcache_sync(scodec->regmap); in sun8i_codec_runtime_resume()
215 regcache_cache_only(scodec->regmap, true); in sun8i_codec_runtime_suspend()
216 regcache_mark_dirty(scodec->regmap); in sun8i_codec_runtime_suspend()
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| /Linux-v6.1/sound/soc/fsl/ |
| D | fsl_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
42 return -EINVAL; in fsl_asoc_get_dma_channel()
44 if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) { in fsl_asoc_get_dma_channel()
46 return -EINVAL; in fsl_asoc_get_dma_channel()
55 * dai->platform name should already point to an allocated buffer. in fsl_asoc_get_dma_channel()
62 snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn", in fsl_asoc_get_dma_channel()
65 iprop = of_get_property(dma_channel_np, "cell-index", NULL); in fsl_asoc_get_dma_channel()
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| /Linux-v6.1/sound/soc/codecs/ |
| D | jz4760.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
18 #include <sound/soc-dai.h>
19 #include <sound/soc-dapm.h>
166 struct clk *clk; member
173 struct regmap *regmap = jz_codec->regmap; in jz4760_codec_set_bias_level()
199 struct snd_soc_component *codec = dai->component; in jz4760_codec_startup()
208 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4760_codec_startup()
216 struct snd_soc_component *codec = dai->component; in jz4760_codec_shutdown()
219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4760_codec_shutdown()
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| D | jz4770.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
17 #include <sound/soc-dai.h>
18 #include <sound/soc-dapm.h>
182 struct clk *clk; member
189 struct regmap *regmap = jz_codec->regmap; in jz4770_codec_set_bias_level()
219 struct snd_soc_component *codec = dai->component; in jz4770_codec_startup()
227 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4770_codec_startup()
236 struct snd_soc_component *codec = dai->component; in jz4770_codec_shutdown()
239 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4770_codec_shutdown()
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| D | jz4725b.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
145 struct clk *clk; member
149 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0);
170 SOC_SINGLE("High-Pass Filter Capture Switch",
186 SOC_DAPM_ENUM("ADC Source Capture Route", jz4725b_codec_adc_src_enum);
197 struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm); in jz4725b_out_stage_enable()
199 struct regmap *map = icdc->regmap; in jz4725b_out_stage_enable()
218 return -EINVAL; in jz4725b_out_stage_enable()
231 SND_SOC_DAPM_MUX("ADC Source Capture Route", SND_SOC_NOPM, 0, 0,
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| /Linux-v6.1/drivers/clk/qcom/ |
| D | clk-regmap-mux-div.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * struct mux_div_clk - combined mux/divider clock
18 * @src_width: number of bits in source select
19 * @src_shift: lowest bit of source select field
23 * @clkr: handle between common and hardware-specific interfaces
37 struct clk *pclk;
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| /Linux-v6.1/drivers/watchdog/ |
| D | davinci_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2006-2013 Texas Instruments.
21 #include <linux/clk.h>
24 #define MODULE_NAME "DAVINCI-WDT: "
60 * @base - base io address of WD device
61 * @clk - source clock of WDT
62 * @wdd - hold watchdog device as is in WDT core
66 struct clk *clk; member
77 wdt_freq = clk_get_rate(davinci_wdt->clk); in davinci_wdt_start()
79 /* disable, internal clock source */ in davinci_wdt_start()
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| /Linux-v6.1/drivers/gpu/drm/mcde/ |
| D | mcde_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) ST-Ericsson SA 2013
52 /* One-shot mode: flow stops after one frame */
57 * Command mode with bus turn-around (BTA) and tearing effect
63 /* Video mode with the formatter itself as sync source */
65 /* DPI video with the formatter itsels as sync source */
85 struct clk *mcde_clk;
86 struct clk *lcd_clk;
87 struct clk *hdmi_clk;
89 struct clk *fifoa_clk;
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| /Linux-v6.1/drivers/pwm/ |
| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
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