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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_clk.c52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk… in rv1_dump_clk_registers() argument
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) in rv1_dump_clk_registers()
60 bypass->dcfclk_bypass = 0; in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) in rv1_dump_clk_registers()
71 bypass->dispclk_pypass = 0; in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) in rv1_dump_clk_registers()
77 bypass->dprefclk_bypass = 0; in rv1_dump_clk_registers()
/Linux-v5.15/sound/soc/codecs/
Dwm8990.c104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
[all …]
Dwm8400.c140 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
142 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
144 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
146 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
148 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
150 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
154 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
156 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
158 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
160 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
[all …]
Dwm8991.c176 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
178 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
180 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
182 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
184 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
186 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
190 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
192 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
194 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
196 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
[all …]
Dtlv320aic3x.c330 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
335 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
340 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
345 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
350 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
355 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
361 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
368 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
375 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
430 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
[all …]
Dwm9712.c166 SOC_SINGLE("PCBeep Bypass Headphone Volume", AC97_PC_BEEP, 12, 7, 1),
167 SOC_SINGLE("PCBeep Bypass Speaker Volume", AC97_PC_BEEP, 8, 7, 1),
168 SOC_SINGLE("PCBeep Bypass Phone Volume", AC97_PC_BEEP, 4, 7, 1),
288 WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPL_MIXER, 5),
290 WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPL_MIXER, 3),
291 WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPL_MIXER, 2),
298 WM9712_HP_MIXER_CTRL("PCBeep Bypass Switch", HPR_MIXER, 5),
300 WM9712_HP_MIXER_CTRL("Phone Bypass Switch", HPR_MIXER, 3),
301 WM9712_HP_MIXER_CTRL("Line Bypass Switch", HPR_MIXER, 2),
308 SOC_DAPM_SINGLE("PCBeep Bypass Switch", AC97_PC_BEEP, 11, 1, 1),
[all …]
Dadau1373.c603 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
604 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
605 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
606 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
627 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
628 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
629 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
630 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
636 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
637 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
[all …]
Dtlv320dac33.c465 "Bypass", "Mode 1", "Mode 7"
510 /* Analog bypass */
544 /* Analog bypass */
545 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
547 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
555 * For DAPM path, when only the anlog bypass path is enabled, and the
559 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
560 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
580 /* Analog bypass */
581 {"Analog Left Bypass", "Switch", "LINEL"},
[all …]
Disabelle.c414 SOC_SINGLE("ATX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
416 SOC_SINGLE("ATX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
418 SOC_SINGLE("ARX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
420 SOC_SINGLE("ARX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
422 SOC_SINGLE("ARX3 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
424 SOC_SINGLE("ARX4 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
426 SOC_SINGLE("ARX5 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
428 SOC_SINGLE("ARX6 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
430 SOC_SINGLE("VRX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
432 SOC_SINGLE("VRX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
[all …]
Dwm8971.c142 SOC_DOUBLE_R("Bypass Left Playback Volume", WM8971_LOUTM1,
144 SOC_DOUBLE_R("Bypass Right Playback Volume", WM8971_ROUTM1,
146 SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8971_MOUTM1,
194 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_LOUTM1, 7, 1, 0),
196 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_LOUTM2, 7, 1, 0),
202 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_ROUTM1, 7, 1, 0),
204 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_ROUTM2, 7, 1, 0),
210 SOC_DAPM_SINGLE("Left Bypass Switch", WM8971_MOUTM1, 7, 1, 0),
212 SOC_DAPM_SINGLE("Right Bypass Switch", WM8971_MOUTM2, 7, 1, 0),
286 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
[all …]
/Linux-v5.15/include/linux/
Dirqbypass.h3 * IRQ offload/bypass manager
18 * The IRQ bypass manager is a simple set of lists and callbacks that allows
20 * consumers (ex. virtualization hardware that allows IRQ bypass or offload)
32 * struct irq_bypass_producer - IRQ bypass producer definition
33 * @node: IRQ bypass manager private list management
41 * The IRQ bypass producer structure represents an interrupt source for
42 * participation in possible host bypass, for instance an interrupt vector
58 * struct irq_bypass_consumer - IRQ bypass consumer definition
59 * @node: IRQ bypass manager private list management
66 * The IRQ bypass consumer structure represents an interrupt sink for
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
72 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
74 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
75 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
158 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass
159 uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/
Dfrontend.json3 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
13 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
23 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
34 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
44 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
55 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
65 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
76 …(DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
88 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
99 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellde/
Dfrontend.json8 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
18 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
29 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
39 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
50 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
60 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
71 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
83 …(DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
94 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
105 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
[all …]
/Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/
Dfrontend.json8 …e uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instr…
18 …n Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also…
29 …nstruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
39 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
50 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
60 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
71 …(IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
83 …(DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
94 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
105 …e (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
[all …]
/Linux-v5.15/include/trace/events/
Dbcache.h124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
145 TP_printk("%d,%d %s %llu + %u hit %u bypass %u",
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
[all …]
/Linux-v5.15/drivers/regulator/
Danatop-regulator.c30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
/Linux-v5.15/virt/lib/
Dirqbypass.c3 * IRQ offload/bypass manager
14 * bypass.
23 MODULE_DESCRIPTION("IRQ bypass manager utility module");
78 * irq_bypass_register_producer - register IRQ bypass producer
129 * irq_bypass_unregister_producer - unregister IRQ bypass producer
173 * irq_bypass_register_consumer - register IRQ bypass consumer
225 * irq_bypass_unregister_consumer - unregister IRQ bypass consumer
/Linux-v5.15/drivers/clk/at91/
Dsckc.c122 bool bypass, in at91_clk_register_slow_osc() argument
148 if (bypass) in at91_clk_register_slow_osc()
374 bool bypass; in at91sam9x5_sckc_register() local
394 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
398 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
405 xtal_name, 1200000, bypass, bits); in at91sam9x5_sckc_register()
468 bool bypass; in of_sam9x60_sckc_setup() local
484 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
486 xtal_name, 5000000, bypass, in of_sam9x60_sckc_setup()
/Linux-v5.15/drivers/clk/imx/
Dclk-sscg-pll.c75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
365 /* set bypass here too since the parent might be the same */ in clk_sscg_pll_set_rate()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
/Linux-v5.15/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_color.c61 * As per DRM documentation, blocks should be in hardware bypass when their
63 * considered as putting the respective block into bypass mode.
68 * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ...
69 * CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass
95 * like a bypass LUT.
402 * No CRTC RGM means we can just put the block into bypass in amdgpu_dm_update_crtc_color_mgmt()
434 /* Bypass CTM. */ in amdgpu_dm_update_crtc_color_mgmt()
527 /* ...Otherwise we can just bypass the DGM block. */ in amdgpu_dm_update_plane_color_mgmt()
/Linux-v5.15/drivers/base/regmap/
Dregcache.c43 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
59 /* Bypass the cache access till data read from HW */ in regcache_hw_init()
344 bool bypass; in regcache_sync() local
349 /* Remember the initial bypass state */ in regcache_sync()
350 bypass = map->cache_bypass; in regcache_sync()
382 /* Restore the bypass state */ in regcache_sync()
384 map->cache_bypass = bypass; in regcache_sync()
413 bool bypass; in regcache_sync_region() local
419 /* Remember the initial bypass state */ in regcache_sync_region()
420 bypass = map->cache_bypass; in regcache_sync_region()
[all …]
/Linux-v5.15/drivers/clk/ti/
Dclkt_dpll.c175 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
178 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
179 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
188 * Each set bit in the mask corresponds to a bypass value equal in _omap2_dpll_is_in_bypass()
217 /* Reparent the struct clk in case the dpll is in bypass */ in omap2_init_dpll_parent()
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
233 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
235 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
248 /* Return bypass rate if DPLL is bypassed */ in omap2_get_dpll_rate()
/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt7 (reference clock and bypass clock), with digital phase locked
38 and second entry bypass clock
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
81 ti,low-power-bypass;
/Linux-v5.15/Documentation/devicetree/bindings/power/supply/
Dbq25980.yaml55 ti,bypass-ovp-limit-microvolt:
62 ti,bypass-ocp-limit-microamp:
68 ti,bypass-enable:
70 description: Enables bypass mode at boot time

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