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/Linux-v5.15/drivers/phy/marvell/
Dphy-mvebu-a3700-utmi.c9 * Marvell A3700 UTMI PHY driver
21 /* Armada 3700 UTMI PHY registers */
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
88 struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy); in mvebu_a3700_utmi_phy_power_on() local
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
102 writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
105 regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32), in mvebu_a3700_utmi_phy_power_on()
111 reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); in mvebu_a3700_utmi_phy_power_on()
[all …]
Dphy-mvebu-cp110-utmi.c8 * Marvell CP110 UTMI PHY driver
24 /* CP110 UTMI register macro definetions */
167 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_off() local
170 /* Power down UTMI PHY port */ in mvebu_cp110_utmi_phy_power_off()
171 regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id), in mvebu_cp110_utmi_phy_power_off()
175 int test = regmap_test_bits(utmi->syscon, in mvebu_cp110_utmi_phy_power_off()
178 /* skip PLL shutdown if there are active UTMI PHY ports */ in mvebu_cp110_utmi_phy_power_off()
183 /* PLL Power down if all UTMI PHYs are down */ in mvebu_cp110_utmi_phy_power_off()
184 regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK); in mvebu_cp110_utmi_phy_power_off()
192 struct mvebu_cp110_utmi *utmi = port->priv; in mvebu_cp110_utmi_phy_power_on() local
[all …]
DKconfig40 tristate "Marvell A3700 UTMI driver"
46 Enable this to support Marvell A3700 UTMI PHY driver.
71 tristate "Marvell CP110 UTMI driver"
76 Enable this to support Marvell CP110 UTMI PHY driver.
DMakefile8 obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
11 obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o
/Linux-v5.15/drivers/clk/at91/
Dclk-utmi.c42 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_prepare() local
51 * the utmi clock. in clk_utmi_prepare()
78 if (utmi->regmap_sfr) { in clk_utmi_prepare()
79 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, in clk_utmi_prepare()
86 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_prepare()
88 while (!clk_utmi_ready(utmi->regmap_pmc)) in clk_utmi_prepare()
96 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_is_prepared() local
98 return clk_utmi_ready(utmi->regmap_pmc); in clk_utmi_is_prepared()
103 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_unprepare() local
105 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, in clk_utmi_unprepare()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmarvell,armada-cp110-utmi-phy.yaml5 $id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
8 title: Marvell Armada CP110/CP115 UTMI PHY
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
19 UTMI PHY0 --------/
23 UTMI PHY1 --------\
28 const: marvell,cp110-utmi-phy
50 Each UTMI PHY port must be represented as a sub-node.
77 cp0_utmi: utmi@580000 {
78 compatible = "marvell,cp110-utmi-phy";
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Dnvidia,tegra20-usb-phy.txt13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
21 - timer: The timeout clock (clk_m). Present if phy_type == utmi.
22 - utmi-pads: The clock needed to access the UTMI pad control registers.
23 Present if phy_type == utmi.
32 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
38 Required PHY timing params for utmi phy, for all chips:
53 Required PHY timing params for utmi phy, only on Tegra30 and above:
70 - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
[all …]
Dmarvell,armada-3700-utmi-phy.yaml5 $id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#"
8 title: Marvell Armada UTMI/UTMI+ PHY
17 a slightly different UTMI PHY.
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
48 compatible = "marvell,armada-3700-utmi-host-phy";
Dphy-stm32-usbphyc.yaml11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
24 |_ UTMI switch_______| OTG controller
98 The value is used to select UTMI switch output.
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
/Linux-v5.15/Documentation/devicetree/bindings/usb/
Dusb.yaml36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
42 enum: [utmi, utmi_wide, ulpi, serial, hsic]
Domap-usb.txt13 specifying ULPI and UTMI respectively.
55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
77 utmi-mode = <2>;
Dhisilicon,histb-xhci.txt13 "utmi": for utmi clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
Datmel-usb.txt37 - clocks: Should reference the peripheral and the UTMI clocks
40 "usb_clk" for the UTMI clock
46 clocks = <&utmi>, <&uhphs_clk>;
115 clocks = <&utmi>, <&udphs_clk>;
Dsnps,dwc3.yaml57 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
229 snps,is-utmi-l1-suspend:
241 High-Speed PHY interface selection between UTMI+ and ULPI when the
244 enum: [utmi, ulpi]
/Linux-v5.15/drivers/media/usb/dvb-usb-v2/
Drtl28xxu.h197 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201 #define USB_UTMI_TST 0x2F80 /* UTMI test */
202 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */
/Linux-v5.15/drivers/usb/phy/
Dphy-tegra-usb.c261 "Failed to enable UTMI-pads clock: %d\n", ret); in utmip_pad_open()
270 "Failed to initialize UTMI-pads reset: %d\n", ret); in utmip_pad_open()
277 "Failed to assert UTMI-pads reset: %d\n", ret); in utmip_pad_open()
286 "Failed to deassert UTMI-pads reset: %d\n", ret); in utmip_pad_open()
302 "Failed to enable UTMI-pads clock: %d\n", ret); in utmip_pad_close()
309 "Failed to assert UTMI-pads reset: %d\n", ret); in utmip_pad_close()
1037 "Failed to read USB UTMI parameter %s: %d\n", in read_utmi_param()
1056 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n"); in utmi_phy_probe()
1061 * Note that UTMI pad registers are shared by all PHYs, therefore in utmi_phy_probe()
1067 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n"); in utmi_phy_probe()
[all …]
/Linux-v5.15/include/soc/at91/
Datmel-sfr.h18 #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
19 #define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */
/Linux-v5.15/arch/arm64/boot/dts/marvell/
Darmada-8040-db.dts164 phy-names = "utmi";
179 phy-names = "usb", "utmi";
325 phy-names = "utmi";
333 phy-names = "utmi";
/Linux-v5.15/arch/arm/boot/dts/
Dtegra30.dtsi964 phy_type = "utmi";
977 phy_type = "utmi";
981 clock-names = "reg", "pll_u", "utmi-pads";
983 reset-names = "usb", "utmi-pads";
996 nvidia,has-utmi-pad-registers;
1004 phy_type = "utmi";
1016 phy_type = "utmi";
1020 clock-names = "reg", "pll_u", "utmi-pads";
1022 reset-names = "usb", "utmi-pads";
1042 phy_type = "utmi";
[all …]
Dtegra114.dtsi697 phy_type = "utmi";
709 phy_type = "utmi";
713 clock-names = "reg", "pll_u", "utmi-pads";
715 reset-names = "usb", "utmi-pads";
727 nvidia,has-utmi-pad-registers;
735 phy_type = "utmi";
747 phy_type = "utmi";
751 clock-names = "reg", "pll_u", "utmi-pads";
753 reset-names = "usb", "utmi-pads";
Dtegra124.dtsi1085 phy_type = "utmi";
1097 phy_type = "utmi";
1101 clock-names = "reg", "pll_u", "utmi-pads";
1103 reset-names = "usb", "utmi-pads";
1115 nvidia,has-utmi-pad-registers;
1123 phy_type = "utmi";
1135 phy_type = "utmi";
1139 clock-names = "reg", "pll_u", "utmi-pads";
1141 reset-names = "usb", "utmi-pads";
1160 phy_type = "utmi";
[all …]
Dtegra20.dtsi750 phy_type = "utmi";
764 phy_type = "utmi";
769 clock-names = "reg", "pll_u", "timer", "utmi-pads";
771 reset-names = "usb", "utmi-pads";
781 nvidia,has-utmi-pad-registers;
806 reset-names = "usb", "utmi-pads";
815 phy_type = "utmi";
827 phy_type = "utmi";
832 clock-names = "reg", "pll_u", "timer", "utmi-pads";
834 reset-names = "usb", "utmi-pads";
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi1113 phy_type = "utmi";
1126 phy_type = "utmi";
1130 clock-names = "reg", "pll_u", "utmi-pads";
1132 reset-names = "usb", "utmi-pads";
1144 nvidia,has-utmi-pad-registers;
1152 phy_type = "utmi";
1165 phy_type = "utmi";
1169 clock-names = "reg", "pll_u", "utmi-pads";
1171 reset-names = "usb", "utmi-pads";
1190 phy_type = "utmi";
[all …]
/Linux-v5.15/drivers/usb/chipidea/
Dci_hdrc_tegra.c113 * The 1st USB controller contains some UTMI pad registers that are in tegra_usb_reset_controller()
117 rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads"); in tegra_usb_reset_controller()
119 dev_warn(dev, "can't get utmi-pads reset from the PHY\n"); in tegra_usb_reset_controller()
123 * PHY driver performs UTMI-pads reset in a case of a in tegra_usb_reset_controller()

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