| /Linux-v6.1/include/asm-generic/ |
| D | tlb.h | 2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
53 * Finish in particular will issue a (final) TLB invalidate and free
88 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets
91 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees
108 * flush the entire TLB irrespective of the range. For instance
127 * returns the smallest TLB entry size unmapped in this range.
140 * This might be useful if your architecture has size specific TLB
[all …]
|
| /Linux-v6.1/mm/ |
| D | mmu_gather.c | 14 #include <asm/tlb.h>
18 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
22 batch = tlb->active; in tlb_next_batch()
24 tlb->active = batch->next; in tlb_next_batch()
28 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch()
35 tlb->batch_count++; in tlb_next_batch()
40 tlb->active->next = batch; in tlb_next_batch()
41 tlb->active = batch; in tlb_next_batch()
46 static void tlb_batch_pages_flush(struct mmu_gather *tlb) in tlb_batch_pages_flush() argument
50 for (batch = &tlb->local; batch && batch->nr; batch = batch->next) { in tlb_batch_pages_flush()
[all …]
|
| /Linux-v6.1/arch/arm64/include/asm/ |
| D | tlb.h | 3 * Based on arch/arm/include/asm/tlb.h
20 static void tlb_flush(struct mmu_gather *tlb);
22 #include <asm-generic/tlb.h>
29 static inline int tlb_get_level(struct mmu_gather *tlb) in tlb_get_level() argument
32 if (tlb->freed_tables) in tlb_get_level()
35 if (tlb->cleared_ptes && !(tlb->cleared_pmds || in tlb_get_level()
36 tlb->cleared_puds || in tlb_get_level()
37 tlb->cleared_p4ds)) in tlb_get_level()
40 if (tlb->cleared_pmds && !(tlb->cleared_ptes || in tlb_get_level()
41 tlb->cleared_puds || in tlb_get_level()
[all …]
|
| /Linux-v6.1/arch/s390/include/asm/ |
| D | tlb.h | 6 * TLB flushing on s390 is complicated. The following requirement
14 * AND PURGE instruction that purges the TLB."
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
37 #include <asm-generic/tlb.h>
41 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
44 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, in __tlb_remove_page_size() argument
51 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
53 __tlb_flush_mm_lazy(tlb->mm); in tlb_flush()
58 * page table from the tlb.
[all …]
|
| /Linux-v6.1/arch/loongarch/include/asm/ |
| D | tlb.h | 13 * TLB Invalidate Flush
26 * TLB R/W operations.
49 /* Invalid all tlb */
51 /* Invalid current tlb */
53 /* Invalid all global=1 lines in current tlb */
55 /* Invalid all global=0 lines in current tlb */
57 /* Invalid global=0 and matched asid lines in current tlb */
59 /* Invalid addr with global=0 and matched asid in current tlb */
61 /* Invalid addr with global=1 or matched asid in current tlb */
63 /* Invalid matched gid in guest tlb */
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | translation.json | 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
[all …]
|
| /Linux-v6.1/arch/mips/kvm/ |
| D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
137 * We don't want to get reserved instruction exceptions for missing tlb in kvm_vz_host_tlb_inv()
153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping.
155 * @gpa: Guest virtual address in a TLB mapped guest segment.
[all …]
|
| /Linux-v6.1/arch/x86/include/asm/ |
| D | tlb.h | 6 static inline void tlb_flush(struct mmu_gather *tlb);
8 #include <asm-generic/tlb.h>
10 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
13 unsigned int stride_shift = tlb_get_unmap_shift(tlb); in tlb_flush()
15 if (!tlb->fullmm && !tlb->need_flush_all) { in tlb_flush()
16 start = tlb->start; in tlb_flush()
17 end = tlb->end; in tlb_flush()
20 flush_tlb_mm_range(tlb->mm, start, end, stride_shift, tlb->freed_tables); in tlb_flush()
24 * While x86 architecture in general requires an IPI to perform TLB
29 * below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
|
| /Linux-v6.1/arch/arm/include/asm/ |
| D | tlb.h | 3 * arch/arm/include/asm/tlb.h
8 * to use the "invalidate whole tlb" rather than "invalidate single
9 * tlb" for this.
23 #define tlb_flush(tlb) ((void) tlb) argument
25 #include <asm-generic/tlb.h>
37 #include <asm-generic/tlb.h>
40 __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr) in __pte_free_tlb() argument
50 __tlb_adjust_range(tlb, addr - PAGE_SIZE, 2 * PAGE_SIZE); in __pte_free_tlb()
53 tlb_remove_table(tlb, pte); in __pte_free_tlb()
57 __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr) in __pmd_free_tlb() argument
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| D | cache.json | 129 "PublicDescription": "Level 1 PLD TLB refill",
132 "BriefDescription": "Level 1 PLD TLB refill"
135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa…
138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar…
141 "PublicDescription": "Level 1 TLB flush",
144 "BriefDescription": "Level 1 TLB flush"
147 "PublicDescription": "Level 2 TLB access",
150 "BriefDescription": "Level 2 TLB access"
153 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c…
156 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /Linux-v6.1/Documentation/x86/ |
| D | tlb.rst | 4 The TLB
10 1. Flush the entire TLB with a two-instruction sequence. This is
11 a quick operation, but it causes collateral damage: TLB entries
17 damage to other TLB entries.
23 entire TLB than doing 2^48/PAGE_SIZE individual flushes.
24 2. The contents of the TLB. If the TLB is empty, then there will
28 3. The size of the TLB. The larger the TLB, the more collateral
29 damage we do with a full flush. So, the larger the TLB, the
32 4. The microarchitecture. The TLB has become a multi-level
37 especially the contents of the TLB during a given flush. The
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | virtual-memory.json | 9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
46 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
70 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
94 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
113 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
119 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
131 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | virtual-memory.json | 9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
46 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
70 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
94 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
113 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
119 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
131 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /Linux-v6.1/Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
24 - altr,tlb-num-entries: Specifies the number of entries in the TLB.
25 - altr,tlb-ptr-sz: Specifies size of TLB pointer.
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
52 altr,tlb-num-ways = <16>;
53 altr,tlb-num-entries = <128>;
54 altr,tlb-ptr-sz = <7>;
58 altr,fast-tlb-miss-addr = <0xc7fff400>;
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | virtual-memory.json | 9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
46 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
82 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
101 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
107 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
119 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
131 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | virtual-memory.json | 9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
26 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
43 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
54 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
76 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
99 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
110 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
121 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
[all …]
|
| /Linux-v6.1/arch/sh/mm/ |
| D | tlb-urb.c | 2 * arch/sh/mm/tlb-urb.c
4 * TLB entry wiring helpers for URB-equipped parts.
14 #include <asm/tlb.h>
18 * Load the entry for 'addr' into the TLB and wire the entry.
32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry()
39 * Insert this entry into the highest non-wired TLB slot (via in tlb_wire_entry()
46 /* Load the entry into the TLB */ in tlb_wire_entry()
62 * Unwire the last wired TLB entry.
65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
81 * Make sure we're not trying to unwire a TLB entry when none in tlb_unwire_entry()
|
| D | Makefile | 30 debugfs-$(CONFIG_CPU_SH4) += tlb-debugfs.o
31 tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
32 tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o
33 tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o
34 obj-y += $(tlb-y)
|
| /Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| D | cache.json | 72 "PublicDescription": "Level 1 PLD TLB refill",
75 "BriefDescription": "Level 1 PLD TLB refill"
78 "PublicDescription": "Level 1 CP15 TLB refill",
81 "BriefDescription": "Level 1 CP15 TLB refill"
84 "PublicDescription": "Level 1 TLB flush",
87 "BriefDescription": "Level 1 TLB flush"
90 "PublicDescription": "Level 2 TLB access",
93 "BriefDescription": "Level 2 TLB access"
96 "PublicDescription": "Level 2 TLB miss",
99 "BriefDescription": "Level 2 TLB miss"
|
| /Linux-v6.1/arch/ia64/include/asm/ |
| D | tlb.h | 5 * Based on <asm-generic/tlb.h>.
11 * Removing a translation from a page table (including TLB-shootdown) is a four-step
22 * The Linux kernel defines several platform-specific hooks for TLB-shootdown. When
26 * tlb <- tlb_gather_mmu(mm); // start unmap for address space MM
29 * tlb_start_vma(tlb, vma);
31 * tlb_remove_tlb_entry(tlb, pte, address);
33 * tlb_remove_page(tlb, page);
36 * tlb_end_vma(tlb, vma);
39 * tlb_finish_mmu(tlb); // finish unmap for address space MM
48 #include <asm-generic/tlb.h>
|
| /Linux-v6.1/include/linux/ |
| D | io-pgtable.h | 26 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
28 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
29 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
32 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
33 * single page. IOMMUs that cannot batch TLB invalidation
60 * @tlb: TLB management callbacks for this set of tables.
100 const struct iommu_flush_ops *tlb; member
185 * the callback routines in cfg->tlb.
194 * live, but the TLB can be dirty.
225 if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_all) in io_pgtable_tlb_flush_all()
[all …]
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| /Linux-v6.1/arch/arm/mm/ |
| D | tlb-v7.S | 3 * linux/arch/arm/mm/tlb-v7.S
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
22 * Invalidate a range of TLB entries in the specified address space.
47 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
49 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
51 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
63 * Invalidate a range of kernel TLB entries
76 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
[all …]
|
