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/Linux-v6.6/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5332-dwc3
18 - qcom,ipq6018-dwc3
19 - qcom,ipq8064-dwc3
20 - qcom,ipq8074-dwc3
21 - qcom,ipq9574-dwc3
22 - qcom,msm8953-dwc3
23 - qcom,msm8994-dwc3
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Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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Drockchip,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
24 - $ref: snps,dwc3.yaml#
31 - rockchip,rk3328-dwc3
32 - rockchip,rk3568-dwc3
40 - rockchip,rk3328-dwc3
41 - rockchip,rk3568-dwc3
42 - const: snps,dwc3
99 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
Domap-usb.txt46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
Dfsl,imx8mq-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
Dti,keystone-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
Dintel,keembay-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
41 $ref: snps,dwc3.yaml#
61 compatible = "intel,keembay-dwc3";
72 compatible = "snps,dwc3";
Ddwc3-xilinx.yaml4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
82 $ref: snps,dwc3.yaml#
113 compatible = "xlnx,zynqmp-dwc3";
127 compatible = "snps,dwc3";
Damlogic,meson-g12a-usb-ctrl.yaml8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
84 - $ref: snps,dwc3.yaml#
229 dwc3: usb@ff500000 {
230 compatible = "snps,dwc3";
Drockchip,rk3399-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
14 const: rockchip,rk3399-dwc3
57 $ref: snps,dwc3.yaml#
82 compatible = "rockchip,rk3399-dwc3";
96 compatible = "snps,dwc3";
/Linux-v6.6/drivers/usb/dwc3/
DMakefile5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
46 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
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Ddwc3-haps.c3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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Ddwc3-imx8mp.c3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
53 struct platform_device *dwc3; member
101 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
104 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
109 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) in dwc3_imx8mp_wakeup_enable()
112 else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_wakeup_enable()
131 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
222 dwc3_np = of_get_compatible_child(node, "snps,dwc3"); in dwc3_imx8mp_probe()
225 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
231 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
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Ddwc3-pci.c3 * dwc3-pci.c - PCI Specific glue layer
68 * @dwc3: child dwc3 platform_device
75 struct platform_device *dwc3; member
266 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
270 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
271 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
287 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
294 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
297 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
299 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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Dcore.c49 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
121 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
256 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
272 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
279 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
347 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); in dwc3_core_soft_reset()
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Ddwc3-qcom.c4 * Inspired by dwc3-of-simple.c
70 struct platform_device *dwc3; member
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init()
310 struct dwc3 *dwc; in dwc3_qcom_is_host()
315 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed()
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code in dwc3_qcom_read_usb2_speed()
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
675 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
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Ddrd.c19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq()
72 struct dwc3 *dwc = _dwc; in dwc3_otg_irq()
93 static void dwc3_otgregs_init(struct dwc3 *dwc) in dwc3_otgregs_init()
137 static int dwc3_otg_get_irq(struct dwc3 *dwc) in dwc3_otg_get_irq()
167 void dwc3_otg_init(struct dwc3 *dwc) in dwc3_otg_init()
186 void dwc3_otg_exit(struct dwc3 *dwc) in dwc3_otg_exit()
195 void dwc3_otg_host_init(struct dwc3 *dwc) in dwc3_otg_host_init()
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Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans()
92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
195 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
253 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
263 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
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Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc) in dwc3_ep0_reset_state()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
230 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
249 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
280 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
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Dcore.h77 /* DWC3 registers memory space boundries */
682 struct dwc3 *dwc;
730 struct dwc3 *dwc;
922 * @status: internal dwc3 request status tracking
972 * struct dwc3 - representation of our controller
1060 * @sysdev_is_parent: true when dwc3 device has a parent driver
1068 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1128 struct dwc3 { struct
1348 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) argument
1499 * DWC3 Features to be used as Driver Data
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Ddwc3-of-simple.c3 * dwc3-of-simple.c - OF glue layer for simple integrations
9 * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
52 if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) in dwc3_of_simple_probe()
172 { .compatible = "rockchip,rk3399-dwc3" },
173 { .compatible = "sprd,sc9860-dwc3" },
174 { .compatible = "allwinner,sun50i-h6-dwc3" },
175 { .compatible = "hisilicon,hi3670-dwc3" },
176 { .compatible = "intel,keembay-dwc3" },
186 .name = "dwc3-of-simple",
Dgadget.h18 struct dwc3;
93 * @reason: cancelled reason for the dwc3 request
110 void dwc3_ep0_interrupt(struct dwc3 *dwc,
112 void dwc3_ep0_out_start(struct dwc3 *dwc);
113 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
114 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
120 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
125 * @dep: dwc3 endpoint
146 static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) in dwc3_gadget_dctl_write_safe()
Ddwc3-st.c3 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
5 * This is a small driver for the dwc3 to provide the glue logic
14 * Inspired by dwc3-omap.c and dwc3-exynos.c.
78 * struct st_dwc3 - dwc3-st driver private structure
254 child = of_get_compatible_child(node, "snps,dwc3"); in st_dwc3_probe()
256 dev_err(&pdev->dev, "failed to find dwc3 core node\n"); in st_dwc3_probe()
264 dev_err(dev, "failed to add dwc3 core\n"); in st_dwc3_probe()
270 dev_err(dev, "failed to find dwc3 core device\n"); in st_dwc3_probe()
357 { .compatible = "st,stih407-dwc3" },
367 .name = "usb-st-dwc3",
Ddwc3-keystone.c3 * dwc3-keystone.c - Keystone Specific Glue layer
136 if (of_device_is_compatible(node, "ti,am654-dwc3")) in kdwc3_probe()
158 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in kdwc3_probe()
190 if (!of_device_is_compatible(node, "ti,am654-dwc3")) in kdwc3_remove()
203 { .compatible = "ti,keystone-dwc3", },
204 { .compatible = "ti,am654-dwc3" },
213 .name = "keystone-dwc3",
220 MODULE_ALIAS("platform:keystone-dwc3");
/Linux-v6.6/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-dwc3-glue.yaml4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
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