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/Linux-v5.15/arch/arm/mm/
Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
99 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
128 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
133 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
135 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
Dproc-arm946.S57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-xsc3.S149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
Dcache-v6.S40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
143 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
Dproc-arm940.S50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
Dproc-fa526.S108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
Dcache-v4wt.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
Dproc-arm926.S109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dproc-arm925.S143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
403 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dproc-mohawk.S92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
Dproc-xscale.S148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
237 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
244 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
268 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
285 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
290 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
311 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
473 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
Dtlb-v6.S48 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
76 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
84 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
Dproc-arm922.S110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
355 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
112 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
170 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
Dproc-v6.S61 mcr p15, 0, r1, c7, c5, 4 @ ISB
102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
154 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
170 mcr p15, 0, ip, c7, c5, 4 @ ISB
206 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
Dproc-feroceon.S123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
475 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dproc-arm920.S108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
351 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie.txt18 TEGRA194_POWER_DOMAIN_PCIEX8A: C5
55 5: C5
92 In Tegra194, Only controllers C0, C4 & C5 support EP mode.
102 It is mandatory for C5 controller and optional for other controllers.
105 It is mandatory for C5 controller and optional for other controllers.
112 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
113 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
125 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
128 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
135 NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
/Linux-v5.15/arch/arm/include/asm/hardware/
Dcp14.h47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
/Linux-v5.15/arch/arm/include/asm/
Dtlbflush.h323 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_all()
370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_mm()
376 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); in __local_flush_tlb_mm()
424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_page()
431 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
479 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
481 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_kernel_page()
485 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
534 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); in __local_flush_bp_all()
[all …]
Ddcc.h20 asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg" in __dcc_getchar()
29 asm volatile("mcr p14, 0, %0, c0, c5, 0 @ write a char" in __dcc_putchar()
/Linux-v5.15/arch/arm/boot/compressed/
Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
743 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
744 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
748 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
758 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
771 mcr p15, 0, r0, c5, c0, 0 @ access permission
901 mcr p15, 0, r0, c7, c5, 4 @ ISB
905 mcr p15, 0, r0, c7, c5, 4 @ ISB
1169 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1203 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
[all …]
/Linux-v5.15/arch/arm/include/asm/vdso/
Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/Linux-v5.15/tools/testing/selftests/net/
Droute_localnet.sh42 ping -c5 -I veth0 127.25.3.14
59 ping -c5 -I veth0 127.25.3.14

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