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Searched full:armpll (Results 1 – 23 of 23) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dbrcm,iproc-clocks.yaml15 An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
32 - brcm,hr2-armpll
33 - brcm,nsp-armpll
76 - brcm,cygnus-armpll
77 - brcm,nsp-armpll
93 - brcm,cygnus-armpll
111 armpll crystal N/A N/A
150 - brcm,hr2-armpll
[all …]
Dzynq-7000.txt41 0: armpll
96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
/Linux-v5.15/arch/arm/boot/dts/
Dbcm-cygnus-clock.dtsi45 armpll: armpll@19000000 { label
47 compatible = "brcm,cygnus-armpll";
56 clocks = <&armpll>;
65 clocks = <&armpll>;
Dbcm63138.dtsi56 clocks = <&armpll>;
65 clocks = <&armpll>;
125 armpll: armpll@20000 { label
127 compatible = "brcm,bcm63138-armpll";
Dbcm-hr2.dtsi70 compatible = "brcm,hr2-armpll";
Dzynq-7000.dtsi306 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
Dbcm5301x.dtsi55 compatible = "brcm,nsp-armpll";
Dbcm-nsp.dtsi88 compatible = "brcm,nsp-armpll";
/Linux-v5.15/drivers/cpufreq/
Dmediatek-cpufreq.c207 struct clk *armpll = clk_get_parent(cpu_clk); in mtk_cpufreq_set_target() local
260 ret = clk_set_rate(armpll, freq_hz); in mtk_cpufreq_set_target()
264 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
270 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
289 clk_set_rate(armpll, old_freq_hz); in mtk_cpufreq_set_target()
290 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
/Linux-v5.15/drivers/clk/zynq/
Dclkc.c50 armpll, ddrpll, iopll, enumerator
237 cpu_parents[0] = clk_output_name[armpll]; in zynq_clk_setup()
238 cpu_parents[1] = clk_output_name[armpll]; in zynq_clk_setup()
243 periph_parents[2] = clk_output_name[armpll]; in zynq_clk_setup()
259 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
/Linux-v5.15/drivers/clk/bcm/
Dclk-bcm63xx.c22 CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
Dclk-hr2.c27 CLK_OF_DECLARE(hr2_armpll, "brcm,hr2-armpll", hr2_armpll_init);
DMakefile8 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
Dclk-nsp.c43 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
Dclk-cygnus.c55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt7629.c308 "armpll",
310 "armpll"
338 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
Dclk-mt7622.c110 "armpll",
112 "armpll"
331 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
Dclk-mt2701.c125 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
478 "armpll",
937 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
Dclk-mt8516.c439 "armpll",
773 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
Dclk-mt8167.c629 "armpll",
1019 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
Dclk-mt6765.c752 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8516.dtsi98 clock-names = "cpu", "intermediate", "armpll";