| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
29 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
39 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …ublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1…
13 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and f…
23 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins…
33 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v5.15/drivers/block/paride/ |
| D | kbic.c | 5 This is a low-level driver for the KBIC-951A and KBIC-971A
9 required for the 971A interferes with the correct operation of
10 the 951A, so this driver registers itself twice, once for
35 #define j44(a,b) ((((a>>4)&0x0f)|(b&0xf0))^0x88) argument
36 #define j53(w) (((w>>3)&0x1f)|((w>>4)&0xe0))
47 { int a, b, s; in kbic_read_regr() local
53 case 0: w0(regr|0x18|s); w2(4); w2(6); w2(4); w2(1); w0(8); in kbic_read_regr()
54 a = r1(); w0(0x28); b = r1(); w2(4); in kbic_read_regr()
55 return j44(a,b); in kbic_read_regr()
57 case 1: w0(regr|0x38|s); w2(4); w2(6); w2(4); w2(5); w0(8); in kbic_read_regr()
[all …]
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| D | epat.c | 31 #define j44(a,b) (((a>>4)&0x0f)+(b&0xf0)) argument
32 #define j53(a,b) (((a>>3)&0x1f)+((b<<4)&0xe0)) argument
57 case 2: w0(0x60+r); w2(1); w0(val); w2(4); in epat_write_regr()
61 case 4: in epat_write_regr()
70 { int a, b, r; in epat_read_regr() local
77 a = r1(); w2(4); b = r1(); in epat_read_regr()
78 return j44(a,b); in epat_read_regr()
80 case 1: w0(0x40+r); w2(1); w2(4); in epat_read_regr()
81 a = r1(); b = r2(); w0(0xff); in epat_read_regr()
82 return j53(a,b); in epat_read_regr()
[all …]
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| /Linux-v5.15/arch/arc/kernel/ |
| D | ctx_sw.c | 9 * So we cheat a bit by writing almost similar code in inline-asm.
10 * -This is a hacky way of doing things, but there is no other simple way.
18 #define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4)
29 "st.a r13, [sp, -4] \n\t" in __switch_to()
30 "st.a r14, [sp, -4] \n\t" in __switch_to()
31 "st.a r15, [sp, -4] \n\t" in __switch_to()
32 "st.a r16, [sp, -4] \n\t" in __switch_to()
33 "st.a r17, [sp, -4] \n\t" in __switch_to()
34 "st.a r18, [sp, -4] \n\t" in __switch_to()
35 "st.a r19, [sp, -4] \n\t" in __switch_to()
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| /Linux-v5.15/arch/s390/lib/ |
| D | uaccess.c | 70 "6: jz 4f\n" in copy_from_user_mvcos()
75 "2: la %4,4095(%1)\n"/* %4 = ptr + 4095 */ in copy_from_user_mvcos()
76 " nr %4,%3\n" /* %4 = (ptr + 4095) & -4096 */ in copy_from_user_mvcos()
77 " slgr %4,%1\n" in copy_from_user_mvcos()
78 " clgr %0,%4\n" /* copy crosses next page boundary? */ in copy_from_user_mvcos()
80 "3: .insn ss,0xc80000000000,0(%4,%2),0(%1),0\n" in copy_from_user_mvcos()
81 "7: slgr %0,%4\n" in copy_from_user_mvcos()
83 "4: slgr %0,%0\n" in copy_from_user_mvcos()
86 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcos()
108 "3: la %4,255(%1)\n" /* %4 = ptr + 255 */ in copy_from_user_mvcp()
[all …]
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| /Linux-v5.15/arch/x86/crypto/ |
| D | twofish-x86_64-asm_64.S | 14 #define b_offset 4
27 /* define a few register aliases to allow macro substitution */
60 * a input register containing a (rotated 16)
64 * operations on a and b are interleaved to increase performance
66 #define encrypt_round(a,b,c,d,round)\ argument
68 mov s1(%r11,%rdi,4),%r8d;\
69 movzx a ## B, %edi;\
70 mov s2(%r11,%rdi,4),%r9d;\
73 xor s2(%r11,%rdi,4),%r8d;\
74 movzx a ## H, %edi;\
[all …]
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| D | twofish-i586-asm_32.S | 17 #define ctx 4 /* Twofish context structure */
20 #define b_offset 4
33 /* define a few register aliases to allow macro substitution */
61 * a input register containing a (rotated 16)
65 * operations on a and b are interleaved to increase performance
67 #define encrypt_round(a,b,c,d,round)\ argument
70 mov s1(%ebp,%edi,4),d ## D;\
71 movzx a ## B, %edi;\
72 mov s2(%ebp,%edi,4),%esi;\
75 xor s2(%ebp,%edi,4),d ## D;\
[all …]
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| D | sha256-avx2-asm.S | 11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
48 # This code schedules 2 blocks at a time, with 4 lanes per block
102 a = %eax define
115 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
139 # Rotate values of symbols a...h
149 b = a
150 a = TMP_ define
156 mov a, y3 # y3 = a # MAJA
161 or c, y3 # y3 = a|c # MAJA
[all …]
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| /Linux-v5.15/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-rgb.rst | 9 These formats encode each pixel as a triplet of RGB values. They are packed
12 bits required to store a pixel is not aligned to a byte boundary, the data is
20 or a permutation thereof, collectively referred to as alpha formats) depend on
24 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
25 but can set the alpha bit to a user-configurable value, the
28 the value specified by that control. Otherwise a corresponding format without
34 filled with meaningful values by applications. Otherwise a corresponding format
38 Formats that contain padding bits are named XRGB (or a permutation thereof).
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
46 respectively. 'a' denotes bits of the alpha component (if supported by the
[all …]
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| D | pixfmt-packed-yuv.rst | 15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
17 'U') and red chroma (also known as 'V') components respectively. 'A'
22 4:4:4 Subsampling
25 These formats do not subsample the chroma components and store each pixels as a
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
44 .. flat-table:: Packed YUV 4:4:4 Image Formats (less than 8bpc)
[all …]
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| /Linux-v5.15/include/uapi/drm/ |
| D | drm_fourcc.h | 4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 3 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
11 "CounterHTOff": "0,1,2,3,4,5,6,7"
14 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
21 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
32 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
36 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
43 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 9 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
[all …]
|
| /Linux-v5.15/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 9 …event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
[all …]
|
| /Linux-v5.15/drivers/staging/greybus/Documentation/ |
| D | sysfs-bus-greybus | 3 KernelVersion: 4.XX
7 where N is a dynamically assigned 1-based id.
11 KernelVersion: 4.XX
18 KernelVersion: 4.XX
21 A Module M on the bus N, where M is the 1-byte interface
26 KernelVersion: 4.XX
29 Writing a non-zero argument to this attibute disables the
34 KernelVersion: 4.XX
37 The ID of a Greybus module, corresponding to the ID of its
42 KernelVersion: 4.XX
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
40 "Counter": "0,1,2,3,4,5,6,7",
46 "PEBScounters": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
61 "PEBScounters": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
76 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
9 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
17 "Counter": "0,1,2,3,4,5,6,7",
23 "PEBScounters": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
51 "PEBScounters": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7",
64 "PEBScounters": "0,1,2,3,4,5,6,7",
65 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
71 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
[all …]
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| D | memory.json | 3 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
9 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
17 "Counter": "0,1,2,3,4,5,6,7",
20 "PEBScounters": "0,1,2,3,4,5,6,7",
35 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
43 "Counter": "0,1,2,3,4,5,6,7",
50 "PEBScounters": "0,1,2,3,4,5,6,7",
66 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
74 "Counter": "0,1,2,3,4,5,6,7",
77 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 99 …ber of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be deliver…
105 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
111 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
141 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
147 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
155 "Counter": "0,1,2,3,4,5,6,7",
158 "PEBScounters": "0,1,2,3,4,5,6,7",
159 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
167 "Counter": "0,1,2,3,4,5,6,7",
171 "PEBScounters": "0,1,2,3,4,5,6,7",
[all …]
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| /Linux-v5.15/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 19 #define MC_FW_STATE_BOOTING (4)
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
51 /* Check whether an mcfw version (in host order) belongs to a bootloader */
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
87 * The protocol requires one response to be delivered for every request, a
102 #define MCDI_HEADER_SEQ_WIDTH 4
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
130 * Both events share a common structure:
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
[all …]
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| /Linux-v5.15/Documentation/input/devices/ |
| D | elantech.rst | 18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
[all …]
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| /Linux-v5.15/tools/testing/selftests/bpf/prog_tests/ |
| D | btf.c | 97 * struct A {
103 * int q[4][8];
111 BTF_TYPE_INT_ENC(0, BTF_INT_SIGNED, 0, 32, 4), /* [1] */
117 BTF_TYPE_ARRAY_ENC(1, 1, 8), /* [4] */
118 /* struct A { */ /* [5] */
123 BTF_MEMBER_ENC(NAME_TBD, 4, 128),/* int p[8] */
124 BTF_MEMBER_ENC(NAME_TBD, 6, 384),/* int q[4][8] */
127 /* int[4][8] */
128 BTF_TYPE_ARRAY_ENC(4, 1, 4), /* [6] */
135 .str_sec = "\0A\0m\0n\0o\0p\0q\0r\0E\0E0\0E1",
[all …]
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| /Linux-v5.15/drivers/net/wireguard/selftest/ |
| D | allowedips.c | 3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
8 * DEBUG_PRINT_TRIE_GRAPHVIZ to be 1, then every time there's a full tree in
9 * memory, it will be printed out as KERN_DEBUG in a format that can be passed
12 * randomized tests done against a trivial implementation, which may take
13 * upwards of a half-hour to complete. There's no set of users who should be
127 if (node->ip_version == 4) { in horrible_mask_self()
190 node->ip_version = 4; in horrible_allowedips_insert_v4()
220 if (node->ip_version == 4 && horrible_match_v4(node, ip)) in horrible_allowedips_lookup_v4()
287 prandom_bytes(ip, 4); in randomized_test()
301 memcpy(mutated, ip, 4); in randomized_test()
[all …]
|
