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Searched +full:0 +full:x4105 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.15/Documentation/devicetree/bindings/net/
Dmdio-mux-gpio.yaml44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
47 #size-cells = <0>;
52 #size-cells = <0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
[all …]
/Linux-v5.15/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
Docteon_68xx.dts16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
/Linux-v5.15/drivers/net/wireless/rsi/
Drsi_sdio.h32 BUFFER_FULL = 0x0,
33 BUFFER_AVAILABLE = 0x2,
34 FIRMWARE_ASSERT_IND = 0x3,
35 MSDU_PACKET_PENDING = 0x4,
36 UNKNOWN_INT = 0XE
40 #define PKT_BUFF_SEMI_FULL 0
51 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3
52 #define RSI_FN1_INT_REGISTER 0xf9
53 #define RSI_INT_ENABLE_REGISTER 0x04
54 #define RSI_INT_ENABLE_MASK 0xfc
[all …]
/Linux-v5.15/drivers/gpu/drm/gma500/
Dpsb_drv.c45 * 0x8086 = Intel Corporation
56 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
57 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
59 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
60 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
61 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
62 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
63 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
64 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
65 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
[all …]
/Linux-v5.15/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/Linux-v5.15/drivers/net/wireless/ath/ath9k/
Dpci.c27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
34 0x0029,
36 0x2096),
40 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
44 0x002A,
46 0x1C71),
49 0x002A,
51 0xE01F),
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]