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12

/Linux-v5.15/arch/arm64/boot/dts/ti/
Dk3-am65.dtsi68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
Dk3-j7200.dtsi39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
25 reg = <0x00 0x40a00000 0x00 0x100>;
34 reg = <0x00 0x41c00000 0x00 0x80000>;
35 ranges = <0x0 0x00 0x41c00000 0x80000>;
42 reg = <0x0 0x40b00000 0x0 0x100>;
45 #size-cells = <0>;
53 reg = <0x0 0x40300000 0x0 0x400>;
58 #size-cells = <0>;
[all …]
Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x0 0x00 0x41c00000 0x100000>;
[all …]
Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x40f00000 0x00 0x20000>;
42 ranges = <0x00 0x00 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x00 0x43000014 0x00 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x00 0x00 0x41c00000 0x100000>;
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dsram.h58 #define OMAP2_SRAM_PA 0x40200000
59 #define OMAP3_SRAM_PA 0x40200000
/Linux-v5.15/arch/arm/mach-pxa/include/mach/
Dregs-uart.h11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
[all …]
Duncompress.h12 #define FFUART_BASE (0x40100000)
13 #define BTUART_BASE (0x40200000)
14 #define STUART_BASE (0x40700000)
67 uart_base = 0x10000000; /* nCS4 */ in arch_decomp_setup()
69 uart_is_pxa = 0; in arch_decomp_setup()
/Linux-v5.15/arch/powerpc/platforms/cell/spufs/
Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0, 0($SP)
74 brsl $0, main
78 * stop-and-signal with code=0.
84 stop 0x0
[all …]
Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
Dspu_restore.c15 #define LS_SIZE 0x40000 /* 256K (in bytes) */
25 #define BR_INSTR 0x327fff80 /* br -4 */
26 #define NOP_INSTR 0x40200000 /* nop */
27 #define HEQ_INSTR 0x7b000000 /* heq $0, $0 */
28 #define STOP_INSTR 0x00000000 /* stop 0x0 */
29 #define ILLEGAL_INSTR 0x00800000 /* illegal instr */
30 #define RESTORE_COMPLETE 0x00003ffc /* stop 0x3ffc */
34 unsigned int ls = (unsigned int)&regs_spill[0]; in fetch_regs_from_mem()
36 unsigned int tag_id = 0; in fetch_regs_from_mem()
37 unsigned int cmd = 0x40; /* GET */ in fetch_regs_from_mem()
[all …]
Dspu_save_dump.h_shipped7 0x20805000,
8 0x20805201,
9 0x20805402,
10 0x20805603,
11 0x20805804,
12 0x20805a05,
13 0x20805c06,
14 0x20805e07,
15 0x20806008,
16 0x20806209,
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/usb/
Dnxp,isp1760.yaml61 reg = <0x40200000 0x100000>;
/Linux-v5.15/arch/arm/boot/dts/
Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
Dmps2.dtsi53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
116 #clock-cells = <0>;
[all …]
Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
67 reg = <0x1>;
69 clock-frequency = <0>;
[all …]
/Linux-v5.15/arch/arm/mach-pxa/
Dviper.c111 * Therefore we do two reads. The first time we write 0 to the
113 * 0xff first. If the two reads do not match or they read back as 0xff
114 * or 0x00 then we have version 1 hardware.
123 VIPER_VERSION = 0; in viper_hw_version()
125 VIPER_VERSION = 0xff; in viper_hw_version()
128 v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1; in viper_hw_version()
138 return 0; in viper_cpu_suspend()
166 int i = 0; in viper_set_core_cpu_voltage()
167 unsigned int divisor = 0; in viper_set_core_cpu_voltage()
171 v = "1.0"; divisor = 0xfff; in viper_set_core_cpu_voltage()
[all …]
Dzeus.c63 0, /* ISA irq #0, invalid */
64 0, /* ISA irq #1, invalid */
65 0, /* ISA irq #2, invalid */
66 1 << 0, /* ISA irq #3 */
71 0, /* ISA irq #8, invalid */
72 0, /* ISA irq #9, invalid */
80 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)]; in zeus_irq_to_bitmask()
85 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0); in zeus_bit_to_irq()
151 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { in zeus_init_irq()
169 [0] = { /* NOR Flash (up to 64MB) */
[all …]
Ddevices.c55 [0] = {
56 .start = 0x41100000,
57 .end = 0x41100fff,
67 static u64 pxamci_dmamask = 0xffffffffUL;
71 .id = 0,
74 .coherent_dma_mask = 0xffffffff,
96 [0] = {
97 .start = 0x40600000,
98 .end = 0x4060ffff,
108 static u64 udc_dma_mask = ~(u32)0;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsm8250.dtsi78 #clock-cells = <0>;
86 #clock-cells = <0>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
97 reg = <0x0 0x0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
116 reg = <0x0 0x100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
132 reg = <0x0 0x200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
/Linux-v5.15/sound/pci/mixart/
Dmixart_mixer.c24 0xc2c00000, /* [000] -96.0 dB */
25 0xc2bf0000, /* [001] -95.5 dB */
26 0xc2be0000, /* [002] -95.0 dB */
27 0xc2bd0000, /* [003] -94.5 dB */
28 0xc2bc0000, /* [004] -94.0 dB */
29 0xc2bb0000, /* [005] -93.5 dB */
30 0xc2ba0000, /* [006] -93.0 dB */
31 0xc2b90000, /* [007] -92.5 dB */
32 0xc2b80000, /* [008] -92.0 dB */
33 0xc2b70000, /* [009] -91.5 dB */
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]

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